mirror of https://github.com/openXC7/prjxray.git
163 lines
5.7 KiB
Python
163 lines
5.7 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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import json
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# Set to true to enable additional tags useful for tracing bit toggles.
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DEBUG_FUZZER = False
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def bitfilter(frame, word):
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if frame < 30 or frame > 37:
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return False
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return True
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def handle_data_width(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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site = d['ologic_loc']
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for opt in [2, 3, 4, 5, 6, 7, 8]:
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segmk.add_site_tag(
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site, 'OSERDES.DATA_WIDTH.W{}'.format(opt), d['DATA_WIDTH'] == opt)
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if verilog.unquote(d['DATA_RATE_OQ']) == 'DDR':
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# DDR + WIDTH 6/8 have some overlapping bits, create a feature.
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OVERLAPPING_WIDTHS = [6, 8]
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segmk.add_site_tag(
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site, 'OSERDES.DATA_WIDTH.DDR.W{}'.format(
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'_'.join(map(str, OVERLAPPING_WIDTHS))),
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d['DATA_WIDTH'] in OVERLAPPING_WIDTHS)
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else:
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# SDR + WIDTH 2/4/5/6 have some overlapping bits, create a feature.
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OVERLAPPING_WIDTHS = [2, 4, 5, 6]
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segmk.add_site_tag(
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site, 'OSERDES.DATA_WIDTH.SDR.W{}'.format(
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'_'.join(map(str, OVERLAPPING_WIDTHS))),
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d['DATA_WIDTH'] in OVERLAPPING_WIDTHS)
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def main():
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print("Loading tags")
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segmk = Segmaker("design.bits")
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with open('params.jl', 'r') as f:
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design = json.load(f)
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for d in design:
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site = d['ologic_loc']
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handle_data_width(segmk, d)
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segmk.add_site_tag(site, 'OSERDES.IN_USE', d['use_oserdese2'])
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if d['use_oserdese2']:
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segmk.add_site_tag(site, 'OQUSED', 1)
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for opt in ['SDR', 'DDR']:
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segmk.add_site_tag(
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site, 'OSERDES.DATA_RATE_OQ.{}'.format(opt),
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verilog.unquote(d['DATA_RATE_OQ']) == opt)
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for opt in ['BUF', 'SDR', 'DDR']:
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segmk.add_site_tag(
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site, 'OSERDES.DATA_RATE_TQ.{}'.format(opt),
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verilog.unquote(d['DATA_RATE_TQ']) == opt)
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for opt in ['SRVAL_OQ', 'SRVAL_TQ', 'INIT_OQ', 'INIT_TQ']:
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segmk.add_site_tag(site, opt, d[opt])
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segmk.add_site_tag(site, 'Z' + opt, 1 ^ d[opt])
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for opt in ['CLK', 'CLKDIV']:
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if d['{}_USED'.format(opt)]:
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k = 'IS_{}_INVERTED'.format(opt)
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segmk.add_site_tag(site, k, d[k])
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segmk.add_site_tag(
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site, 'ZINV_{}'.format(opt), 1 ^ d[k])
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if d['io']:
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for idx in range(4):
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k = 'IS_T{}_INVERTED'.format(idx + 1)
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segmk.add_site_tag(site, k, d[k])
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segmk.add_site_tag(
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site, 'ZINV_T{}'.format(idx + 1), 1 ^ d[k])
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for idx in range(8):
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k = 'IS_D{}_INVERTED'.format(idx + 1)
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segmk.add_site_tag(site, k, d[k])
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segmk.add_site_tag(
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site, 'ZINV_D{}'.format(idx + 1), 1 ^ d[k])
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for tristate_width in [1, 4]:
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segmk.add_site_tag(
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site,
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'OSERDES.TRISTATE_WIDTH.W{}'.format(tristate_width),
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d['TRISTATE_WIDTH'] == tristate_width)
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for opt in ['MASTER', 'SLAVE']:
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segmk.add_site_tag(
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site, 'OSERDES.SERDES_MODE.{}'.format(opt),
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opt == verilog.unquote(d['OSERDES_MODE']))
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if d['oddr_mux_config'] == 'direct' and d[
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'tddr_mux_config'] == 'direct':
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for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
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segmk.add_site_tag(
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site, 'ODDR.DDR_CLK_EDGE.{}'.format(opt),
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verilog.unquote(d['ODDR_CLK_EDGE']) == opt)
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segmk.add_site_tag(
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site, 'TDDR.DDR_CLK_EDGE.INV',
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d['ODDR_CLK_EDGE'] != d['TDDR_CLK_EDGE'])
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segmk.add_site_tag(
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site, 'TDDR.DDR_CLK_EDGE.ZINV',
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d['ODDR_CLK_EDGE'] == d['TDDR_CLK_EDGE'])
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if 'SRTYPE' in d:
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for opt in ['ASYNC', 'SYNC']:
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segmk.add_site_tag(
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site, 'OSERDES.SRTYPE.{}'.format(opt),
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verilog.unquote(d['SRTYPE']) == opt)
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for opt in ['ASYNC', 'SYNC']:
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segmk.add_site_tag(
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site, 'OSERDES.TSRTYPE.{}'.format(opt),
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verilog.unquote(d['TSRTYPE']) == opt)
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if not d['use_oserdese2']:
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if d['oddr_mux_config'] == 'lut':
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segmk.add_site_tag(site, 'OMUX.D1', 1)
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segmk.add_site_tag(site, 'OQUSED', 1)
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elif d['oddr_mux_config'] == 'direct':
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segmk.add_site_tag(site, 'OMUX.D1', 0)
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elif d['oddr_mux_config'] == 'none' and not d['io']:
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segmk.add_site_tag(site, 'OQUSED', 0)
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segmk.add_site_tag(site, 'TQUSED', d['io'])
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if DEBUG_FUZZER:
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for k in d:
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segmk.add_site_tag(
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site, 'param_' + k + '_' + str(d[k]).replace(
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' ', '').replace('\n', ''), 1)
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segmk.compile(bitfilter=bitfilter)
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segmk.write(allow_empty=True)
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if __name__ == "__main__":
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main()
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