mirror of https://github.com/openXC7/prjxray.git
178 lines
5.7 KiB
Python
178 lines
5.7 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import json
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import csv
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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from prjxray import segmaker
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def isinv_tags(segmk, ps, site, actual_ps):
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# all of these bits are inverted
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ks = [
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('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
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('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
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('IS_REGCLKARDRCLK_INVERTED', 'ZINV_REGCLKARDRCLK'),
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('IS_REGCLKB_INVERTED', 'ZINV_REGCLKB'),
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('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
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('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
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('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
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('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'),
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('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
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('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
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]
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for param, tagname in ks:
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# The CLK inverts sometimes are changed during synthesis, resulting
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# in addition inversions. Take this into account.
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if param in actual_ps:
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tag = 1 ^ verilog.parsei(actual_ps[param])
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elif param == 'IS_REGCLKARDRCLK_INVERTED':
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if verilog.parsei(ps['DOA_REG']):
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# When DOA_REG == 1, REGCLKARDRCLK follows the CLKARDCLK setting.
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tag = 1 ^ verilog.parsei(actual_ps['IS_CLKARDCLK_INVERTED'])
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else:
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# When DOA_REG == 0, REGCLKARDRCLK is always inverted.
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tag = 0
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segmk.add_site_tag(site, tagname, tag)
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elif param == 'IS_REGCLKB_INVERTED':
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if verilog.parsei(ps['DOB_REG']):
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# When DOB_REG == 1, REGCLKB follows the CLKBWRCLK setting.
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tag = 1 ^ verilog.parsei(actual_ps['IS_CLKBWRCLK_INVERTED'])
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else:
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# When DOB_REG == 0, REGCLKB is always inverted.
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tag = 0
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else:
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tag = 1 ^ verilog.parsei(ps[param])
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segmk.add_site_tag(site, tagname, tag)
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def bus_tags(segmk, ps, site):
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for param in ("DOA_REG", "DOB_REG"):
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segmk.add_site_tag(site, param, verilog.parsei(ps[param]))
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for param, tagname in [('SRVAL_A', 'ZSRVAL_A'), ('SRVAL_B', 'ZSRVAL_B'),
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('INIT_A', 'ZINIT_A'), ('INIT_B', 'ZINIT_B')]:
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bitstr = verilog.parse_bitstr(ps[param])
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ab = param[-1]
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# Are all bits present?
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hasparity = ps['READ_WIDTH_' + ab] == 18
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for i in range(18):
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# Magic bit positions from experimentation
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# we could just only solve when parity, but this check documents the fine points a bit better
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if hasparity or i not in (1, 9):
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segmk.add_site_tag(
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site, '%s[%u]' % (tagname, i), 1 ^ bitstr[i])
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def rw_width_tags(segmk, ps, site):
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'''
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Y0.READ_WIDTH_A
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width 001_03 001_04 001_05
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1 0 0 0
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2 1 0 0
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4 0 1 0
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9 1 1 0
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18 0 0 1
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'''
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params = ["READ_WIDTH_A", "READ_WIDTH_B", "WRITE_WIDTH_A", "WRITE_WIDTH_B"]
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for param in params:
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set_val = int(ps[param])
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if set_val == 0:
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set_val = 1
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if set_val >= 36:
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continue
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def mk(x):
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return '%s_%u' % (param, x)
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segmaker.add_site_group_zero(
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segmk, site, "",
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[mk(1), mk(2), mk(4), mk(9), mk(18)], mk(1), mk(set_val))
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def write_mode_tags(segmk, ps, site):
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for param in ["WRITE_MODE_A", "WRITE_MODE_B"]:
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set_val = verilog.unquote(ps[param])
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# WRITE_FIRST: no bits set
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segmk.add_site_tag(
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site, '%s_READ_FIRST' % (param), set_val == "READ_FIRST")
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segmk.add_site_tag(
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site, '%s_NO_CHANGE' % (param), set_val == "NO_CHANGE")
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def write_rstreg_priority(segmk, ps, site):
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for param in ["RSTREG_PRIORITY_A", "RSTREG_PRIORITY_B"]:
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set_val = verilog.unquote(ps[param])
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for opt in ["RSTREG", "REGCE"]:
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segmk.add_site_tag(
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site, "{}_{}".format(param, opt), set_val == opt)
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def write_rdaddr_collision(segmk, ps, site):
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for opt in ["DELAYED_WRITE", "PERFORMANCE"]:
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set_val = verilog.unquote(ps['RDADDR_COLLISION_HWCONFIG'])
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segmk.add_site_tag(
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site, "RDADDR_COLLISION_HWCONFIG_{}".format(opt), set_val == opt)
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def run():
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segmk = Segmaker("design.bits")
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clk_inverts = {}
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with open('design.csv', 'r') as f:
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for params in csv.DictReader(f):
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clk_inverts[params['site']] = params
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_RAMB18E1'
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site = verilog.unquote(ps['LOC'])
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bus_tags(segmk, ps, site)
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if ps['RAM_MODE'] == '"TDP"':
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rw_width_tags(segmk, ps, site)
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segmk.add_site_tag(
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site, 'SDP_READ_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
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and int(ps['READ_WIDTH_A']) == 36)
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segmk.add_site_tag(
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site, 'SDP_WRITE_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
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and int(ps['WRITE_WIDTH_B']) == 36)
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if ps['READ_WIDTH_A'] < 36 and ps['WRITE_WIDTH_B'] < 36:
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isinv_tags(segmk, ps, site, clk_inverts[site])
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write_mode_tags(segmk, ps, site)
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write_rstreg_priority(segmk, ps, site)
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write_rdaddr_collision(segmk, ps, site)
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def bitfilter(frame, bit):
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# rw_width_tags() aliasing interconnect on large widths
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return frame not in (20, 21)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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run()
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