mirror of https://github.com/openXC7/prjxray.git
110 lines
3.1 KiB
Python
110 lines
3.1 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker
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from prjxray import util
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segmk = Segmaker("design.bits")
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cache = dict()
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print("Loading tags")
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'''
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module,loc,n
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clb_NFFMUX_O5,SLICE_X12Y100,3
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clb_NFFMUX_AX,SLICE_X13Y100,2
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clb_NFFMUX_O6,SLICE_X14Y100,3
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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module, loc, n = l.split(',')
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n = int(n)
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which = chr(ord('A') + n)
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# clb_NFFMUX_AX => AX
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src = module.replace('clb_NOUTMUX_', '')
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'''
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BOUTMUX
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30_20 30_21 30_22 30_23
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O6 1
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O5 1 1
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XOR 1
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CY 1 1
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F8 1 1
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B5Q 1
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'''
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# if location not included in cache yet: start with assuming all four MUXes are unused.
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if loc not in cache:
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cache[loc] = set("ABCD")
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# rewrite name of F78 source net: MUXes A and C have an F7 input, MUX B has an F8 input
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if src == "F78":
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if which in "AC":
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src = "F7"
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elif which == "B":
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src = "F8"
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else:
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assert 0
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# rewrite name of B5Q source net: It's actually A5Q, B5Q, C5Q, or D5Q
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if src == "B5Q":
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src = which + "5Q"
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# add the 1-tag for this connection
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tag = "%sOUTMUX.%s" % (which, src)
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segmk.add_site_tag(loc, tag, 1)
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# remove this MUX from the cache, preventing generation of 0-tags for this MUX
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cache[loc].remove(which)
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# O6 hack per https://github.com/SymbiFlow/prjxray/issues/243
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segmk.add_site_tag(loc, "%sOUTMUX.%s" % (which, "O6"), src == "O5")
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# create 0-tags for all sources on the remaining (unused) MUXes
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for loc, muxes in cache.items():
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for which in muxes:
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for src in "F7 F8 CY O5 XOR 5Q MC31".split():
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if src == "MC31" and which is not "D": continue
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if src == "F7" and which not in "AC": continue
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if src == "F8" and which not in "B": continue
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if src == "5Q": src = which + "5Q"
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tag = "%sOUTMUX.%s" % (which, src)
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segmk.add_site_tag(loc, tag, 0)
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def bitfilter(frame_idx, bit_idx):
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# locations of A5MA, B5MA, C5MA, D5MA bits. because of the way we generate specimens
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# in this fuzzer we get some aliasing with those bits, so we have to manually exclude
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# them. (Maybe FIXME: read the bit locations from the database files)
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# Since the SRL32 is enabled along with DOUTMUX.MC31, bits related to
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# SRL32 features are masked out.
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if (frame_idx, bit_idx) in [
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(30, 55),
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(31, 55), # D5MA
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(31, 44),
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(31, 45), # C5MA
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(30, 19),
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(31, 19), # B5MA
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(30, 9),
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(31, 8), # A5MA
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(30, 16), # ALUT.SRL
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(1, 23), # WEMUX.CE
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]:
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return False
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return util.bitfilter_clb_mux(frame_idx, bit_idx)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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