mirror of https://github.com/openXC7/prjxray.git
154 lines
3.7 KiB
Python
154 lines
3.7 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import os, random
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random.seed(0)
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from prjxray import util
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from prjxray import verilog
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# INCREMENT is the amount of additional CLBN to be instantiated in the design.
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# This makes the fuzzer compilation more robust against failures.
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INCREMENT = os.getenv('CLBN', 0)
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CLBN = 400 + int(INCREMENT)
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['SLICEL', 'SLICEM']):
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yield site_name
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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lut_bels = ['A6LUT', 'B6LUT', 'C6LUT', 'D6LUT']
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.csv', 'w')
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f.write('module,loc,bel,n\n')
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slices = gen_slices()
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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bel = ''
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if random.randint(0, 1):
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module = 'clb_NCY0_MX'
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else:
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module = 'clb_NCY0_O5'
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n = random.randint(0, 3)
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loc = next(slices)
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bel = lut_bels[n]
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print(' %s' % module)
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print(' #(.LOC("%s"), .BEL("%s"), .N(%d))' % (loc, bel, n))
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print(
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' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
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% (i, 8 * i, 8 * i))
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f.write('%s,%s,%s,%s\n' % (module, loc, bel, n))
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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print(
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'''
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module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X16Y129_FIXME";
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parameter BEL="A6LUT_FIXME";
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parameter N=-1;
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wire [3:0] o;
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wire o6, o5;
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reg [3:0] s;
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always @(*) begin
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s = din[7:4];
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s[N] = o6;
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end
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
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(* LOC=LOC, BEL=\"AFF\", KEEP, DONT_TOUCH *)
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FDRE fdce1(.D(o[0]), .C(clk), .CE(), .R(), .Q());
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(* LOC=LOC, BEL=\"BFF\", KEEP, DONT_TOUCH *)
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FDRE fdce2(.D(o[1]), .C(clk), .CE(), .R(), .Q());
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(* LOC=LOC, BEL=\"CFF\", KEEP, DONT_TOUCH *)
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FDRE fdce3(.D(o[2]), .C(clk), .CE(), .R(), .Q());
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(* LOC=LOC, BEL=\"DFF\", KEEP, DONT_TOUCH *)
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FDRE fdce4(.D(o[3]), .C(clk), .CE(), .R(), .Q());
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endmodule
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module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X16Y129_FIXME";
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parameter BEL="A6LUT_FIXME";
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parameter N=-1;
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wire [3:0] o;
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wire o6, o5;
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reg [3:0] s;
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reg [3:0] di;
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always @(*) begin
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s = din[7:4];
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s[N] = o6;
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di = {din[3:0]};
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di[N] = o5;
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end
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
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(* LOC=LOC, BEL=\"AFF\", KEEP, DONT_TOUCH *)
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FDRE fdce1(.D(o[0]), .C(clk), .CE(), .R(), .Q());
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(* LOC=LOC, BEL=\"BFF\", KEEP, DONT_TOUCH *)
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FDRE fdce2(.D(o[1]), .C(clk), .CE(), .R(), .Q());
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(* LOC=LOC, BEL=\"CFF\", KEEP, DONT_TOUCH *)
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FDRE fdce3(.D(o[2]), .C(clk), .CE(), .R(), .Q());
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(* LOC=LOC, BEL=\"DFF\", KEEP, DONT_TOUCH *)
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FDRE fdce4(.D(o[3]), .C(clk), .CE(), .R(), .Q());
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endmodule
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''')
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