mirror of https://github.com/openXC7/prjxray.git
117 lines
2.9 KiB
Python
117 lines
2.9 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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def gen_sites():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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gridinfo = grid.gridinfo_at_tilename(tile_name)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['MMCME2_ADV']:
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yield tile_name, site_name
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def write_params(params):
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pinstr = 'tile,val,site\n'
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for tile, (site, val) in sorted(params.items()):
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pinstr += '%s,%s,%s\n' % (tile, val, site)
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open('params.csv', 'w').write(pinstr)
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def run():
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print(
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'''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 8;
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localparam integer DOUT_N = 8;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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''')
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params = {}
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# FIXME: can't LOC?
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# only one for now, worry about later
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sites = list(gen_sites())
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for (tile_name, site_name), isone in zip(sites,
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util.gen_fuzz_states(len(sites))):
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# 0 is invalid
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# shift one bit, keeping LSB constant
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CLKOUT1_DIVIDE = {0: 2, 1: 3}[isone]
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params[tile_name] = (site_name, CLKOUT1_DIVIDE)
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC=%s *)
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MMCME2_ADV #(/*.LOC("%s"),*/ .CLKOUT1_DIVIDE(%u)) dut_%s(
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.CLKFBOUT(),
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.CLKFBOUTB(),
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.CLKFBSTOPPED(),
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.CLKINSTOPPED(),
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.CLKOUT0(),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.DO(),
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.DRDY(),
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.LOCKED(),
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.PSDONE(),
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.CLKFBIN(clk),
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.CLKIN1(clk),
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.CLKIN2(clk),
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.CLKINSEL(clk),
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.DADDR(),
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.DCLK(clk),
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.DEN(),
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.DI(),
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.DWE(),
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.PSCLK(clk),
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.PSEN(),
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.PSINCDEC(),
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.PWRDWN(),
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.RST());
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''' % (verilog.quote(site_name), site_name, CLKOUT1_DIVIDE, site_name))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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