mirror of https://github.com/openXC7/prjxray.git
341 lines
8.6 KiB
Python
341 lines
8.6 KiB
Python
import random
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random.seed(0)
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import os
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import re
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def slice_xy():
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'''Return (X1, X2), (Y1, Y2) from XRAY_ROI, exclusive end (for xrange)'''
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# SLICE_X12Y100:SLICE_X27Y149
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# Note XRAY_ROI_GRID_* is something else
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m = re.match(
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r'SLICE_X([0-9]*)Y([0-9]*):SLICE_X([0-9]*)Y([0-9]*)', os.getenv('XRAY_ROI'))
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ms = [int(m.group(i + 1)) for i in range(4)]
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return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
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CLBN = 400
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SLICEX, SLICEY = slice_xy()
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for slicey in range(*SLICEY):
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for slicex in range(*SLICEX):
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,n\n')
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (
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DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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modules = ['clb_NFFMUX_' +
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x for x in ['AX', 'CY', 'F78', 'O5', 'O6', 'XOR']]
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module = random.choice(modules)
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if module == 'clb_NFFMUX_F78':
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n = random.randint(0, 2)
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else:
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n = random.randint(0, 3)
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#n = 0
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loc = next(slices)
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print(' %s' % module)
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print(' #(.LOC("%s"), .N(%d))' % (loc, n))
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print(
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' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (i, 8 * i, 8 * i))
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f.write('%s,%s,%s\n' % (module, loc, n))
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f.close()
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module myLUT8 (input clk, input [7:0] din,
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output lut8o, output lut7bo, output lut7ao,
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//caro: XOR additional result (main output)
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//carco: CLA result (carry module additional output)
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output caro, output carco,
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output bo5, output bo6,
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output wire ff_q, //always connect to output
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input wire ff_d); //mux output net
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parameter LOC="SLICE_FIXME";
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parameter N=-1;
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wire [3:0] caro_all;
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assign caro = caro_all[N];
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wire [3:0] carco_all;
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assign carco = carco_all[N];
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wire [3:0] lutno6;
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wire [3:0] lutno5;
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assign bo5 = lutno5[N];
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assign bo6 = lutno6[N];
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//Outputs does not have to be used, will stay without it
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(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
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MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
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(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(lut7bo), .I0(lutno6[3]), .I1(lutno6[2]), .S(din[6]));
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(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7a (.O(lut7ao), .I0(lutno6[1]), .I1(lutno6[0]), .S(din[6]));
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[3]),
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.O6(lutno6[3]));
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[2]),
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.O6(lutno6[2]));
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_CAFE_0000_0001)
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) lutb (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[1]),
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.O6(lutno6[1]));
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_1CE0_0000_0001)
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) luta (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutno5[0]),
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.O6(lutno6[0]));
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//Outputs do not have to be used, will stay without them
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(caro_all), .CO(carco_all), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI());
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generate
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if (N == 3) begin
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(* LOC=LOC, BEL="DFF", KEEP, DONT_TOUCH *)
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FDPE bff (
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.C(clk),
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.Q(ff_q),
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.CE(1'b1),
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.PRE(1'b0),
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.D(ff_d));
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end
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if (N == 2) begin
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(* LOC=LOC, BEL="CFF", KEEP, DONT_TOUCH *)
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FDPE bff (
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.C(clk),
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.Q(ff_q),
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.CE(1'b1),
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.PRE(1'b0),
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.D(ff_d));
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end
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if (N == 1) begin
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(* LOC=LOC, BEL="BFF", KEEP, DONT_TOUCH *)
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FDPE bff (
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.C(clk),
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.Q(ff_q),
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.CE(1'b1),
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.PRE(1'b0),
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.D(ff_d));
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end
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if (N == 0) begin
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(* LOC=LOC, BEL="AFF", KEEP, DONT_TOUCH *)
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FDPE bff (
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.C(clk),
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.Q(ff_q),
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.CE(1'b1),
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.PRE(1'b0),
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.D(ff_d));
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end
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endgenerate
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endmodule
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//******************************************************************************
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//BFFMUX tests
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module clb_NFFMUX_AX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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parameter N=-1;
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/*
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D: DX
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drawn a little differently
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not a mux control
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becomes a dedicated external signal
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C: CX
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B: BX
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A: AX
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*/
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wire ax = din[6]; //used on MUX8:S, MUX7A:S, and MUX7B:S
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myLUT8 #(.LOC(LOC), .N(N))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(), .carco(),
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.bo5(), .bo6(),
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.ff_q(dout[0]),
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.ff_d(ax));
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endmodule
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module clb_NFFMUX_CY (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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parameter N=-1;
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wire carco;
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myLUT8 #(.LOC(LOC), .N(N))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(), .carco(carco),
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.bo5(), .bo6(),
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.ff_q(dout[0]),
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.ff_d(carco));
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endmodule
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module clb_NFFMUX_F78 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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parameter N=-1;
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wire lut8o, lut7bo, lut7ao;
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/*
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D: N/A (no such mux position)
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C: F7B:O
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B: F8:O
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A: F7A:O
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*/
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wire ff_d;
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generate
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if (N == 3) begin
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//No muxes, so this is undefined
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invalid_configuration invalid_configuration3();
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end else if (N == 2) begin
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assign ff_d = lut7bo;
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end else if (N == 1) begin
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assign ff_d = lut8o;
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end else if (N == 0) begin
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assign ff_d = lut7ao;
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end
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endgenerate
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myLUT8 #(.LOC(LOC), .N(N))
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myLUT8(.clk(clk), .din(din),
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.lut8o(lut8o), .lut7bo(lut7bo), .lut7ao(lut7ao),
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.caro(), .carco(),
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.bo5(), .bo6(),
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.ff_q(dout[0]),
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.ff_d(ff_d));
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endmodule
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module clb_NFFMUX_O5 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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parameter N=-1;
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wire bo5;
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myLUT8 #(.LOC(LOC), .N(N))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(), .carco(),
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.bo5(bo5), .bo6(),
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.ff_q(dout[0]),
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.ff_d(bo5));
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endmodule
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module clb_NFFMUX_O6 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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parameter N=-1;
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wire bo6;
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myLUT8 #(.LOC(LOC), .N(N))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(), .carco(),
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.bo5(), .bo6(bo6),
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.ff_q(dout[0]),
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.ff_d(bo6));
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endmodule
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module clb_NFFMUX_XOR (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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parameter N=-1;
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wire caro;
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myLUT8 #(.LOC(LOC), .N(N))
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myLUT8(.clk(clk), .din(din),
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.lut8o(),
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.caro(caro), .carco(),
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.bo5(), .bo6(bo6),
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.ff_q(dout[0]),
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.ff_d(caro));
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endmodule
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''')
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