mirror of https://github.com/openXC7/prjxray.git
40 lines
673 B
Verilog
40 lines
673 B
Verilog
module top(input clk, stb, di, output do);
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localparam integer DIN_N = 3;
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localparam integer DOUT_N = 1;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [2:0] din, output [0:0] dout);
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(* LOC="SLICE_X12Y102", BEL="AFF" *)
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FDCE ff (
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.C(clk),
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.Q(dout[0]),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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