mirror of https://github.com/openXC7/prjxray.git
113 lines
2.0 KiB
Verilog
113 lines
2.0 KiB
Verilog
`include "setseed.vh"
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`define N 1000
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 6;
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localparam integer DOUT_N = `N;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [5:0] din, output [`N-1:0] dout);
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function [31:0] xorshift32(input [31:0] v);
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begin
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xorshift32 = v;
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xorshift32 = xorshift32 ^ (xorshift32 << 13);
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xorshift32 = xorshift32 ^ (xorshift32 >> 17);
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xorshift32 = xorshift32 ^ (xorshift32 << 5);
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end
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endfunction
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function [31:0] hash32(input [31:0] v);
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begin
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hash32 = v ^ `SEED;
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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end
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endfunction
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function [63:0] hash64(input [31:0] v);
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begin
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hash64[63:32] = hash32(v);
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hash64[31: 0] = hash32(~v);
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end
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endfunction
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genvar i;
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generate
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for (i = 0; i < `N; i = i+1) begin:is
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/*
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wire o5;
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wire o6;
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assign dout[i] = o5 & o6;
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LUT5 #(
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.INIT(32'h8000_0001 + (i << 16) + 1'b1)
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) lut5 (
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.I0(din[0]),
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.I1(din[f1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.O(o5)
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);
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*/
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wire o6;
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wire o2_5;
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wire o2_6;
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//Randomly take out 1/4 iterations
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wire [3:0] hash = hash32(i);
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wire opt_out = |hash;
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assign dout[i] = o6 & o2_5 & o2_6 & opt_out;
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001 + (i << 16))
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) lut6 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(o6)
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);
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001 + (i << 8))
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) lut62 (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o2_5),
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.O6(o2_6)
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);
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end
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endgenerate
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endmodule
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