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prjxray/minitests/clb_ndi1mux
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John McMaster 24c80d9a62 my_RAM64X1D_2 rename for consistency 
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 		2017-12-20 22:46:39 +01:00
..
.gitignore clb_ndi1mux minitest 2017-12-20 22:46:39 +01:00
Makefile clb_ndi1mux minitest 2017-12-20 22:46:39 +01:00
README.txt clb_ndi1mux minitest: prepare for fuzzer 2017-12-20 22:46:39 +01:00
runme.sh clb_ndi1mux minitest 2017-12-20 22:46:39 +01:00
runme.tcl clb_ndi1mux: remove hard coded ROI 2017-12-20 22:46:39 +01:00
top.v my_RAM64X1D_2 rename for consistency 2017-12-20 22:46:39 +01:00

README.txt 

Trying to set SLICEM LUT DI1 inputs
These exist for LUTA, LUTB, and LUTC only
Can either be an external signal, another LUT's data input, or another LUT's carry
Note: mux input pattern is irregular

Result:
The following bits are set for NI but not NMC31:
bit 00_00 ADI1MUX.AI
bit 00_20 BDI1MUX.BI
bit 01_43 BDI1MUX.CI

Additionally, test with unknown DI mux bits don't appear near NI bits
There is something strange going on