mirror of https://github.com/openXC7/prjxray.git
108 lines
3.8 KiB
Tcl
108 lines
3.8 KiB
Tcl
create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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write_checkpoint -force design.dcp
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# write_bitstream -force design.bit
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proc write_clb_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_property IS_PSEUDO $pip]} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] hint"
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} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_int_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects [get_wires $tile/VCC_WIRE]] {
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set wire [regsub {.*/} [get_wires -downhill -of_objects $pip] ""]
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puts $fp "${tile_type}.${wire}.VCC_WIRE default"
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}
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_bram_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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# LOGIC_OUTS pips appear to be always, even thought multiple inputs to
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# the pip junction. Best guess is that the underlying hardware is
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# actually just one wire, and there is no actually junction.
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if [string match "*LOGIC_OUTS*" dst_wire] {
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_clb_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_int_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {BRAM_L BRAM_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_bram_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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