mirror of https://github.com/openXC7/prjxray.git
325 lines
8.2 KiB
Verilog
325 lines
8.2 KiB
Verilog
/*
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SLICEM at the following:
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SLICE_XxY*
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Where Y any value
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x
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Always even (ie 100, 102, 104, etc)
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In our ROI
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x = 6, 8, 10, 12, 14
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SRL16E: LOC + BEL
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SRLC32E: LOC + BEL
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RAM64X1S: LOCs but doesn't BEL
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*/
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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/*
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//BEL works
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my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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*/
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/*
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//BEL works
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//No unknown bits
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my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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*/
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/*
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RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM)
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RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM
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RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM
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RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
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*/
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/*
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seg SEG_CLBLM_L_X10Y127
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bit 01_23
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bit 31_16
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bit 31_17
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bit 31_46
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bit 31_47
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seg SEG_CLBLM_L_X10Y100
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bit 01_23
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bit 31_16
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bit 31_17
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bit 31_46
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bit 31_47
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*/
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my_RAM64X1D2 #(.LOC("SLICE_X6Y100"))
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dut0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_RAM64X1D2 #(.LOC("SLICE_X6Y127"))
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dut1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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my_RAM64X1D2 #(.LOC("SLICE_X12Y100"))
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dut2(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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my_RAM64X1D2 #(.LOC("SLICE_X12Y127"))
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dut3(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
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/*
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my_RAM64M #(.LOC("SLICE_X6Y100"))
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my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X6Y101"))
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my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_RAM64X1S_1 #(.LOC("SLICE_X6Y102"))
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my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_RAM64X2S #(.LOC("SLICE_X6Y103"))
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my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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my_RAM64X1D #(.LOC("SLICE_X6Y104"))
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my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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my_RAM128X1D #(.LOC("SLICE_X6Y105"))
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my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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*/
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endmodule
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module my_RAM64X1D2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1D #(
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.INIT(64'h0),
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.IS_WCLK_INVERTED(1'b0)
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) ramb (
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.DPO(dout[1]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]),
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.A0(din[3]),
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.A1(din[4]),
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.A2(din[5]),
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.A3(din[6]),
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.A4(din[7]),
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.A5(din[0]),
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.DPRA0(din[1]),
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.DPRA1(din[2]),
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.DPRA2(din[3]),
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.DPRA3(din[4]),
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.DPRA4(din[5]),
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.DPRA5(din[6]));
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(* LOC=LOC *)
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RAM64X1D #(
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.INIT(64'h0),
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.IS_WCLK_INVERTED(1'b0)
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) rama (
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.DPO(dout[0]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]),
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.A0(din[3]),
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.A1(din[4]),
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.A2(din[5]),
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.A3(din[6]),
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.A4(din[7]),
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.A5(din[0]),
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.DPRA0(din[1]),
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.DPRA1(din[2]),
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.DPRA2(din[3]),
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.DPRA3(din[4]),
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.DPRA4(din[5]),
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.DPRA5(din[6]));
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endmodule
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module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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wire mc31c;
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(* LOC=LOC, BEL=BEL *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lut (
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.Q(dout[0]),
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.Q31(mc31c),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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endmodule
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module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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SRL16E #(
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) SRL16E (
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.Q(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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endmodule
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module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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RAM64M #(
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) RAM64M (
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.DOA(dout[0]),
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.DOB(dout[1]),
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.DOC(dout[2]),
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.DOD(dout[3]),
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.ADDRA(din[0]),
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.ADDRB(din[1]),
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.ADDRC(din[2]),
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.ADDRD(din[3]),
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.DIA(din[4]),
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.DIB(din[5]),
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.DIC(din[6]),
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.DID(din[7]),
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.WCLK(clk),
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.WE(din[1]));
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endmodule
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module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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(* LOC=LOC, BEL=BEL *)
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RAM64X1S #(
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) RAM64X1S (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_RAM64X1S_1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1S_1 #(
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) RAM64X1S_1 (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_RAM64X2S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X2S #(
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) RAM64X2S (
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.O0(dout[0]),
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.O1(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D0(din[6]),
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.D1(din[7]),
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.WCLK(clk),
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.WE(din[1]));
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endmodule
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module my_RAM64X1D (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1D #(
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.INIT(64'h0),
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.IS_WCLK_INVERTED(1'b0)
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) RAM64X1D (
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.DPO(dout[0]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]),
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.A0(din[3]),
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.A1(din[4]),
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.A2(din[5]),
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.A3(din[6]),
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.A4(din[7]),
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.A5(din[0]),
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.DPRA0(din[1]),
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.DPRA1(din[2]),
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.DPRA2(din[3]),
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.DPRA3(din[4]),
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.DPRA4(din[5]),
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.DPRA5(din[6]));
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endmodule
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module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM128X1D #(
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.INIT(128'h0),
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.IS_WCLK_INVERTED(1'b0)
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) RAM128X1D (
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.DPO(dout[0]),
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.SPO(dout[1]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]));
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endmodule
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