mirror of https://github.com/openXC7/prjxray.git
65 lines
1.6 KiB
Tcl
65 lines
1.6 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc route_delay {} {
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set nets [get_nets]
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foreach net $nets {
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set wire [get_wires -of_objects $net -filter { TILE_NAME =~ "*PCIE_INT_INTERFACE*" && NAME =~ "*IMUX*OUT*" }]
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if { $wire == "" } {
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continue
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}
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if { rand() < 0.30 } {
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continue
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}
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set parts [split $wire "/"]
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set tile_name [lindex $parts 0]
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set wire_name [lindex $parts 1]
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set delay_wire_name [string map {OUT DELAY} $wire_name]
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set delay_node [get_nodes $tile_name/$delay_wire_name]
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if { $delay_node == "" } {
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exit 1
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}
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route_design -unroute -nets $net
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puts "Attempting to route net $net through $delay_node."
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route_via $net [list $delay_node]
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design -directive Quick
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route_design -directive Quick
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route_delay
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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