Keith Rothman de5c8a44a3 Pass configuration from top of utility, rather than implicit variables. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>		2018-11-01 16:18:32 -07:00
..
__init__.py	Generate tile types, site types, tilegrid, tileconn for entire part.	2018-09-26 22:37:33 -07:00
bitstream.py	segprint: move load_bitdata into lib	2018-10-30 10:47:33 -07:00
connections.py	Add ROI annotations and update some missing tilegrid changes.	2018-10-05 18:26:24 -07:00
db.py	Pass configuration from top of utility, rather than implicit variables.	2018-11-01 16:18:32 -07:00
fasm_assembler.py	Fix fasm_assembler for partial tile usage.	2018-10-30 11:08:24 -07:00
fasm_disassembler.py	Assorted fixes.	2018-10-22 09:08:34 -07:00
grid.py	Create design.json that describes roi harness boundry, used for VPR arch def.	2018-10-23 15:16:34 -07:00
lib.py	Really fix find_origin_coordinate	2018-10-12 07:03:37 -07:00
roi.py	Run make format.	2018-10-22 12:32:42 -07:00
segmaker.py	bram: DO_REG, SRVAL, INIT	2018-10-24 18:30:59 -07:00
segment_map.py	Run make format.	2018-10-19 16:19:22 -07:00
site_type.py	Add methods to library.	2018-09-27 13:17:01 -07:00
tile.py	Run make format.	2018-10-19 16:19:22 -07:00
tile_segbits.py	Fix fasm_assembler for partial tile usage.	2018-10-30 11:08:24 -07:00
util.py	Run make format.	2018-10-22 12:32:42 -07:00
verilog.py	101-bram-config: READ/WRITE_WIDTH SRVAL/INIT parity tweaks	2018-10-29 15:29:27 -07:00