mirror of https://github.com/openXC7/prjxray.git
85 lines
2.7 KiB
Tcl
85 lines
2.7 KiB
Tcl
create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set selected_luts {}
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set lut_index 0
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set grid_min_x -1
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set grid_max_x -1
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set grid_min_y -1
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set grid_max_y -1
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
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if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
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if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
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if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
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if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
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set cell [get_cells roi/is[$lut_index].lut]
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set_property LOC [get_sites -of_objects $lut] $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts $lut
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}
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}
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
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set fp [open "tiles.txt" w]
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foreach tile $tiles {
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set type [get_property TYPE $tile]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set sites [get_sites -quiet -of_objects $tile]
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set typed_sites {}
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if [llength $sites] {
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set site_types [get_property SITE_TYPE $sites]
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foreach t $site_types s $sites {
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lappend typed_sites $t $s
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}
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}
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puts $fp "$type $tile $grid_x $grid_y $typed_sites"
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}
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close $fp
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for {set i 0} {$i < $lut_index} {incr i} {
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set cell [get_cells roi/is[$i].lut]
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set orig_init [get_property INIT $cell]
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set new_init [regsub "h8" $orig_init "h0"]
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set_property INIT $new_init $cell
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write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
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set_property INIT $orig_init $cell
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}
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