mirror of https://github.com/openXC7/prjxray.git
447 lines
12 KiB
Python
447 lines
12 KiB
Python
""" Emits top.v's for various BUFHCE routing inputs. """
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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from io import StringIO
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CMT_XY_FUN = util.create_xy_fun(prefix='')
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def read_site_to_cmt():
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""" Yields clock sources and which CMT they route within. """
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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class ClockSources(object):
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""" Class for tracking clock sources.
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Some clock sources can be routed to any CMT, for these, cmt='ANY'.
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For clock sources that belong to a CMT, cmt should be set to the CMT of
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the source.
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"""
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def __init__(self):
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self.sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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def add_clock_source(self, source, cmt):
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""" Adds a source from a specific CMT.
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cmt='ANY' indicates that this source can be routed to any CMT.
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"""
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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self.source_to_cmt[source] = cmt
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def get_random_source(
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self, cmt, uses_left_right_routing=False, no_repeats=False):
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""" Get a random source that is routable to the specific CMT.
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get_random_source will return a source that is either cmt='ANY',
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cmt equal to the input CMT, or the adjecent CMT.
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"""
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choices = []
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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if uses_left_right_routing:
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x, y = CMT_XY_FUN(cmt)
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if x % 2 == 0:
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x += 1
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else:
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x -= 1
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paired_cmt = 'X{}Y{}'.format(x, y)
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if paired_cmt in self.sources:
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for source in self.sources[paired_cmt]:
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if 'BUFHCE' not in source:
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choices.append(source)
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random.shuffle(choices)
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if not uses_left_right_routing:
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return choices[0]
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for source in choices:
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source_cmt = self.source_to_cmt[source]
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if source_cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[source_cmt] = set()
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if no_repeats and source in self.used_sources_from_cmt[source_cmt]:
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continue
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if len(self.used_sources_from_cmt[source_cmt]) >= 14:
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continue
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self.used_sources_from_cmt[source_cmt].add(source)
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return source
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return None
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def get_paired_iobs(db, grid, tile_name):
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""" The two IOB33M's above and below the HCLK row have dedicate clock lines.
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"""
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gridinfo = grid.gridinfo_at_tilename(tile_name)
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loc = grid.loc_of_tilename(tile_name)
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if gridinfo.tile_type.endswith('_L'):
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inc = 1
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else:
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inc = -1
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idx = 1
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while True:
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gridinfo = grid.gridinfo_at_loc((loc.grid_x + inc * idx, loc.grid_y))
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if gridinfo.tile_type == 'HCLK_IOI3':
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break
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idx += 1
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# Move from HCLK_IOI column to IOB column
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idx += 1
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for dy in [-1, -3, 2, 4]:
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iob_loc = (loc.grid_x + inc * idx, loc.grid_y + dy)
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gridinfo = grid.gridinfo_at_loc(iob_loc)
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tile_name = grid.tilename_at_loc(iob_loc)
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assert gridinfo.tile_type.endswith('IOB33')
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for site, site_type in gridinfo.sites.items():
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if site_type == 'IOB33M':
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yield tile_name, site
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def check_allowed(mmcm_pll_dir, cmt):
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""" Check whether the CMT specified is in the allowed direction.
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This function is designed to bias sources to either the left or right
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input lines.
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"""
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if mmcm_pll_dir == 'BOTH':
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return True
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elif mmcm_pll_dir == 'ODD':
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x, y = CMT_XY_FUN(cmt)
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return (x & 1) == 1
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elif mmcm_pll_dir == 'EVEN':
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x, y = CMT_XY_FUN(cmt)
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return (x & 1) == 0
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else:
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assert False, mmcm_pll_dir
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def main():
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"""
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HCLK_CMT switch box has the follow inputs:
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4 IOBs above and below
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14 MMCM outputs
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8 PLL outputs
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4 PHASER_IN outputs
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2 INT connections
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and the following outputs:
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3 PLLE2 inputs
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2 BUFMR inputs
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3 MMCM inputs
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~2 MMCM -> BUFR???
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"""
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clock_sources = ClockSources()
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adv_clock_sources = ClockSources()
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site_to_cmt = dict(read_site_to_cmt())
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db = Database(util.get_db_root())
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grid = db.grid()
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def gen_sites(desired_site_type):
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield tile_name, site
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hclk_cmts = set()
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ins = []
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iobs = StringIO()
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hclk_cmt_tiles = set()
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for tile_name, site in gen_sites('BUFMRCE'):
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cmt = site_to_cmt[site]
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hclk_cmts.add(cmt)
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hclk_cmt_tiles.add(tile_name)
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mmcm_pll_only = random.randint(0, 1)
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mmcm_pll_dir = random.choice(('ODD', 'EVEN', 'BOTH'))
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print(
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'// mmcm_pll_only {} mmcm_pll_dir {}'.format(
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mmcm_pll_only, mmcm_pll_dir))
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for tile_name in sorted(hclk_cmt_tiles):
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for _, site in get_paired_iobs(db, grid, tile_name):
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ins.append('input clk_{site}'.format(site=site))
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if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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clock_sources.add_clock_source(
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'clock_IBUF_{site}'.format(site=site), site_to_cmt[site])
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adv_clock_sources.add_clock_source(
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'clock_IBUF_{site}'.format(site=site), site_to_cmt[site])
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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wire clock_IBUF_{site};
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IBUF #( .IOSTANDARD("LVCMOS33") ) ibuf_{site} (
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.I(clk_{site}),
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.O(clock_IBUF_{site})
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);
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""".format(site=site),
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file=iobs)
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print(
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'''
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module top({inputs});
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy();
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'''.format(inputs=', '.join(ins)))
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print(iobs.getvalue())
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luts = LutMaker()
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wires = StringIO()
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bufhs = StringIO()
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for _, site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = [
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'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(13)
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]
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if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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for clk in mmcm_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print(
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"""
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wire cin1_{site}, cin2_{site}, clkfbin_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV pll_{site} (
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.CLKIN1(cin1_{site}),
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.CLKIN2(cin2_{site}),
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.CLKFBIN(clkfbin_{site}),
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.CLKOUT0({c0}),
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.CLKOUT0B({c1}),
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.CLKOUT1({c2}),
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.CLKOUT1B({c3}),
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.CLKOUT2({c4}),
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.CLKOUT2B({c5}),
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.CLKOUT3({c6}),
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.CLKOUT3B({c7}),
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.CLKOUT4({c8}),
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.CLKOUT5({c9}),
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.CLKOUT6({c10}),
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.CLKFBOUT({c11}),
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.CLKFBOUTB({c12})
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);
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""".format(
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2],
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c3=mmcm_clocks[3],
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c4=mmcm_clocks[4],
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c5=mmcm_clocks[5],
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c6=mmcm_clocks[6],
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c7=mmcm_clocks[7],
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c8=mmcm_clocks[8],
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c9=mmcm_clocks[9],
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c10=mmcm_clocks[10],
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c11=mmcm_clocks[11],
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c12=mmcm_clocks[12],
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))
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for _, site in gen_sites('PLLE2_ADV'):
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pll_clocks = [
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'pll_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(7)
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]
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if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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for clk in pll_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print(
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"""
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wire cin1_{site}, cin2_{site}, clkfbin_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5}, {c6};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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PLLE2_ADV pll_{site} (
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.CLKIN1(cin1_{site}),
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.CLKIN2(cin2_{site}),
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.CLKFBIN(clkfbin_{site}),
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.CLKOUT0({c0}),
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.CLKOUT1({c1}),
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.CLKOUT2({c2}),
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.CLKOUT3({c3}),
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.CLKOUT4({c4}),
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.CLKOUT5({c5}),
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.CLKFBOUT({c6})
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);
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""".format(
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site=site,
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c0=pll_clocks[0],
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c1=pll_clocks[1],
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c2=pll_clocks[2],
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c3=pll_clocks[3],
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c4=pll_clocks[4],
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c5=pll_clocks[5],
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c6=pll_clocks[6],
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))
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for tile_name, site in gen_sites('BUFHCE'):
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print(
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"""
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wire I_{site};
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wire O_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I(I_{site}),
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.O(O_{site})
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);
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""".format(site=site, ),
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file=bufhs)
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if site_to_cmt[site] in hclk_cmts:
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if not mmcm_pll_only:
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clock_sources.add_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site])
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adv_clock_sources.add_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site])
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hclks_used_by_cmt = {}
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for cmt in site_to_cmt.values():
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hclks_used_by_cmt[cmt] = set()
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def check_hclk_src(src, src_cmt):
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if len(hclks_used_by_cmt[src_cmt]
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) >= 12 and src not in hclks_used_by_cmt[src_cmt]:
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return None
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else:
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hclks_used_by_cmt[src_cmt].add(src)
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return src
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if random.random() > .10:
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for tile_name, site in gen_sites('BUFHCE'):
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wire_name = clock_sources.get_random_source(
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site_to_cmt[site],
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uses_left_right_routing=True,
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no_repeats=mmcm_pll_only)
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if wire_name is not None and 'BUFHCE' in wire_name:
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# Looping a BUFHCE to a BUFHCE requires using a hclk in the
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# CMT of the source
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src_cmt = clock_sources.source_to_cmt[wire_name]
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wire_name = check_hclk_src(wire_name, src_cmt)
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if wire_name is None:
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continue
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print(
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"""
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assign I_{site} = {wire_name};""".format(
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site=site,
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wire_name=wire_name,
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),
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file=bufhs)
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for tile_name, site in gen_sites('BUFMRCE'):
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pass
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for l in luts.create_wires_and_luts():
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print(l)
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print(wires.getvalue())
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print(bufhs.getvalue())
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for _, site in gen_sites('BUFR'):
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adv_clock_sources.add_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site])
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print(
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"""
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wire O_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR bufr_{site} (
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.O(O_{site})
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);""".format(site=site))
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for _, site in gen_sites('PLLE2_ADV'):
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for cin in ('cin1', 'cin2', 'clkfbin'):
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if random.random() > .2:
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src = adv_clock_sources.get_random_source(site_to_cmt[site])
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src_cmt = adv_clock_sources.source_to_cmt[src]
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if 'IBUF' not in src and 'BUFR' not in src:
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# Clocks from input pins do not require HCLK's, all other
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# sources route from a global row clock.
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src = check_hclk_src(src, src_cmt)
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if src is None:
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continue
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print(
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"""
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assign {cin}_{site} = {csrc};
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""".format(cin=cin, site=site, csrc=src))
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for _, site in gen_sites('MMCME2_ADV'):
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for cin in ('cin1', 'cin2', 'clkfbin'):
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if random.random() > .2:
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src = adv_clock_sources.get_random_source(site_to_cmt[site])
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src_cmt = adv_clock_sources.source_to_cmt[src]
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if 'IBUF' not in src and 'BUFR' not in src:
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# Clocks from input pins do not require HCLK's, all other
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# sources route from a global row clock.
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src = check_hclk_src(src, src_cmt)
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if src is None:
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continue
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print(
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"""
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assign {cin}_{site} = {csrc};
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""".format(cin=cin, site=site, csrc=src))
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print("endmodule")
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if __name__ == '__main__':
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main()
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