mirror of https://github.com/openXC7/prjxray.git
267 lines
9.4 KiB
Tcl
267 lines
9.4 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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write_checkpoint -force design.dcp
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# write_bitstream -force design.bit
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proc write_clb_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_property IS_PSEUDO $pip]} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] hint"
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} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_int_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects [get_wires $tile/VCC_WIRE]] {
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set wire [regsub {.*/} [get_wires -downhill -of_objects $pip] ""]
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puts $fp "${tile_type}.${wire}.VCC_WIRE default"
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}
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_bram_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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} elseif [string match "*LOGIC_OUTS*" $dst_wire] {
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# LOGIC_OUTS pips appear to be always, even thought multiple inputs to
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# the pip junction. Best guess is that the underlying hardware is
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# actually just one wire, and there is no actual junction.
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foreach src_wire [get_wires -uphill -of_objects $pip] {
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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}
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close $fp
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}
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proc write_hclk_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if [string match "*HCLK_IOI_CK_IGCLK*" $dst_wire] {
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continue
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} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_ioi_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if [string match "*DATAOUT*" $dst_wire] {
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continue
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} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_pss_ppips_db {filename tile} {
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if {[llength $tile] != 0} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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# Skip bi-directional PIPs as they represent hard-wired PS7 connections
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# and are not routable.
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foreach pip [get_pips -of_objects $tile -filter "IS_DIRECTIONAL == 1"] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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}
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proc write_gtp_channel_ppips_db {filename tile tile_suffix} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
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set src_wire [get_wires -uphill -of_objects $pip]
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if {![regexp "IMUX" $src_wire] && ![regexp "GTPE2_CTRL" $src_wire] && ![regexp "GTPE2_CLK" $src_wire]} {
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continue
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}
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puts $fp "${tile_type}${tile_suffix}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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}
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close $fp
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}
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proc write_gtp_int_interface_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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foreach pip [get_pips -of_objects $tile] {
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set dst_wire [get_wires -downhill -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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if {![regexp "IMUX_OUT" $dst_wire]} {
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continue
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}
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if {[regexp "DELAY" $src_wire]} {
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continue
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}
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puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
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}
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close $fp
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}
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foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_clb_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R \
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CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R \
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IO_INT_INTERFACE_R IO_INT_INTERFACE_L \
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BRKH_INT HCLK_L HCLK_R HCLK_CMT \
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CMT_TOP_L_UPPER_T CMT_TOP_L_UPPER_B \
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CMT_TOP_L_LOWER_T CMT_TOP_L_LOWER_B \
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CMT_TOP_R_UPPER_T CMT_TOP_R_UPPER_B \
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CMT_TOP_R_LOWER_T CMT_TOP_R_LOWER_B \
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INT_INTERFACE_L INT_INTERFACE_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_int_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {HCLK_IOI3} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_hclk_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {RIOI3 LIOI3 LIOI3_TBYTETERM RIOI3_TBYTETERM \
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LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_ioi_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {BRAM_L BRAM_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_bram_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {PSS0 PSS1 PSS2 PSS3 PSS4 INT_INTERFACE_PSS_L} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_pss_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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foreach tile_type {GTP_CHANNEL_0 GTP_CHANNEL_1 GTP_CHANNEL_2 GTP_CHANNEL_3 GTP_COMMON} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_gtp_channel_ppips_db "ppips_[string tolower $tile_type].db" $tile ""
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write_gtp_channel_ppips_db "ppips_[string tolower $tile_type]_mid_left.db" $tile "_MID_LEFT"
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write_gtp_channel_ppips_db "ppips_[string tolower $tile_type]_mid_right.db" $tile "_MID_RIGHT"
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}
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}
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foreach tile_type {GTP_INT_INTERFACE} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_gtp_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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