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prjxray/minitests/clb_ndi1mux
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Davide 46c1eef15b renamed all README.txt files to README.md 
Signed-off-by: Davide <davide.toldo@stud.tu-darmstadt.de>
 		2018-02-13 17:00:04 +01:00
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.gitignore clb_ndi1mux minitest 2017-12-20 22:46:39 +01:00
Makefile minitests: centralize common case, cleanup Makefile/runme.sh relation, delete fuzzer artifacts 2017-12-22 13:36:58 -08:00
README.md renamed all README.txt files to README.md 2018-02-13 17:00:04 +01:00
top.v my_RAM64X1D_2 rename for consistency 2017-12-20 22:46:39 +01:00

README.md

Trying to set SLICEM LUT DI1 inputs These exist for LUTA, LUTB, and LUTC only Can either be an external signal, another LUT's data input, or another LUT's carry Note: mux input pattern is irregular

Result: The following bits are set for NI but not NMC31: bit 00_00 ADI1MUX.AI bit 00_20 BDI1MUX.BI bit 01_43 BDI1MUX.CI

Additionally, test with unknown DI mux bits don't appear near NI bits There is something strange going on