mirror of https://github.com/openXC7/prjxray.git
359 lines
7.0 KiB
Python
359 lines
7.0 KiB
Python
import random
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random.seed(0)
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CLBN = 600
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# SLICE_X12Y100
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# SLICE_X27Y149
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SLICEX = (12, 28)
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SLICEY = (100, 150)
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for slicey in range(*SLICEY):
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for slicex in range(*SLICEX):
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 4
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DOUT_N = CLBN * 1
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ffprims = (
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'FD',
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'FD_1',
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'FDC',
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'FDC_1',
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'FDCE',
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'FDCE_1',
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'FDE',
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'FDE_1',
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'FDP',
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'FDP_1',
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'FDPE',
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'FDPE_1',
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'FDR',
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'FDR_1',
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'FDRE',
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'FDRE_1',
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'FDS',
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'FDS_1',
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'FDSE',
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'FDSE_1',
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)
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ffprims = (
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'FDRE',
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'FDSE',
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'FDCE',
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'FDPE',
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)
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ff_bels = (
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'AFF',
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'A5FF',
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'BFF',
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'B5FF',
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'CFF',
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'C5FF',
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'DFF',
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'D5FF',
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)
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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ffprim = random.choice(ffprims)
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# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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loc = next(slices)
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bel = random.choice(ff_bels)
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#bel = "AFF"
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print(' clb_%s' % ffprim)
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print(' #(.LOC("%s"), .BEL("%s"))' % (loc, bel))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i))
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module clb_FD (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y100";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FD ff (
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.C(clk),
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.Q(dout),
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.D(din[0])
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);
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endmodule
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module clb_FD_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y101";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FD_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0])
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);
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endmodule
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module clb_FDC (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y102";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDC ff (
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.C(clk),
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.Q(dout),
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.CLR(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDC_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y103";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDC_1 ff (
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.C(clk),
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.Q(dout),
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.CLR(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDCE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y104";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDCE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDCE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y105";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDCE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y106";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDE ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.CE(din[1])
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);
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endmodule
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module clb_FDE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y107";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDE_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.CE(din[1])
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);
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endmodule
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module clb_FDP (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y108";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDP ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_FDP_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y109";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDP_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_FDPE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y110";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDPE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.PRE(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDPE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y111";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDPE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.PRE(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDR (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y112";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDR ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.R(din[1])
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);
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endmodule
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module clb_FDR_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y113";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDR_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.R(din[1])
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);
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endmodule
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module clb_FDRE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y114";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDRE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.R(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDRE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y115";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDRE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.R(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDS (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y116";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDS ff (
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.C(clk),
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.Q(dout),
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.S(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDS_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y117";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDS_1 ff (
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.C(clk),
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.Q(dout),
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.S(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDSE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y118";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDSE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.S(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDSE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y119";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDSE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.S(din[1]),
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.D(din[2])
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);
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endmodule
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''')
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