mirror of https://github.com/openXC7/prjxray.git
50 lines
1.5 KiB
Python
50 lines
1.5 KiB
Python
#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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segmk = Segmaker("design.bits", verbose=True)
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#segmk.set_def_bt('BLOCK_RAM')
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_RAMB18E1'
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site = verilog.unquote(ps['LOC'])
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#print('site', site)
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# all of these bits are inverted
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ks = [
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('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
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('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
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('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
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('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
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('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
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('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'),
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('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
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('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
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]
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for param, tagname in ks:
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segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
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'''
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parameter DOA_REG = 1'b0;
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parameter DOB_REG = 1'b0;
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parameter SRVAL_A = 18'b0;
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parameter SRVAL_B = 18'b0;
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parameter INIT_A = 18'b0;
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parameter INIT_B = 18'b0;
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'''
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for param, tagname in [('SRVAL_A', 'ZSRVAL_A'), ('SRVAL_B', 'ZSRVAL_B'),
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('INIT_A', 'ZINIT_A'), ('INIT_B', 'ZINIT_B')]:
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bitstr = verilog.parse_bitstr(ps[param])
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for i in range(18):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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segmk.compile()
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segmk.write()
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