mirror of https://github.com/openXC7/prjxray.git
120 lines
4.3 KiB
ReStructuredText
120 lines
4.3 KiB
ReStructuredText
=============
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segbits files
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=============
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The *segbits files* are generated for every FPGA :term:`tile <Tile>` type.
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They store the information about the combinations of bits in the bitstream
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that are responsible for enabling different features inside the :term:`tile <Tile>`.
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The features can be related to enabling some part of the primitive, setting some
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initial state of the block, configuring pin pull-up on output pins, etc.
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Besides the features provided in this file that can be enabled,
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the FPGA chip also has the default configuration. Due to that sometimes there
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is no need for affecting the default configuration.
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Naming convention
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-----------------
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The naming scheme for the segbits files is the following::
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segbits_<tile>.db
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Note that auxiliary ``segbits_<tile>.origin_info.db`` files
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provide additional information about the :term:`fuzzer <Fuzzer>`, which produced the
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:term:`database <Database>` file. This file is optional.
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Every :term:`tile <Tile>` is configured at least by one of three configurational buses
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mentioned in the :doc:`Configuration Section <../../architecture/configuration>`.
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The default bus is called ``CLB_IO_CLK``. If the :term:`tile <Tile>` can also be configured
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by another bus, it has additional ``segbits_<tile>.<bus_name>.db``
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related to that bus.
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Example files:
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- ``segbits_dsp_r.db``
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- ``segbits_bram_l.db`` (configured with default ``CLB_IO_CLK`` bus)
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- ``segbits_bram_l.block_ram.db`` (configured with ``BLOCK_RAM`` bus)
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File format
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-----------
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The file consists of lines containing the information about the feature
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and the list of bits that should be enabled/disabled to provide the feature's
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functionality::
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<feature> <bit_list>
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where:
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- ``<feature>`` is of the form ``<feature_name>.<feature_addr>``
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- ``<bit_list>`` is the list of bits. Each bit is of the form
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``<frame_address_offset>_<bit_possition>``. If the bit has the ``!``
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mark in front of it, that means it should be set to **0** for feature configuration,
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otherwise it should be set to **1**.
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The names of the features are arbitrary. However, the naming convention allows for quick identifaction of the functionality that is being configured.
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The feature names are used during the generation of the :doc:`FASM <../../../../fasm/docs/specification>` file.
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Feature naming conventions
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--------------------------
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PIPs
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^^^^
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The ``<feature>`` names for interconnect :term:`PIPs <PIP>` are stored in the
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``segbits_int_l.db`` and ``segbits_int_r.db`` database files. The features that
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enable interconnect :term:`PIPs <PIP>` have the following syntax::
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<tile_type>.<destination_wire>.<source_wire>.
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For example, consider the following entry in ``segbits_int_l.db``::
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INT_L.NL1BEG1.NN6END2 07_32 12_33
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CLBs
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^^^^
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The ``<feature>`` names for CLB tiles use a dot-separated hierarchy.
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For example::
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CLBLL_L.SLICEL_X0.ALUT.INIT[00]
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This entry documents the initialization bits of the *LSB LUT* for the *ALUT* in
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the *SLICEL_X0* within a *CLBLL_L tile.*
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Example
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-------
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Below there is a part of the ``segbits_liob33_l.db`` file for the *artix7*
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architecture. The file describes the *CLBLL* :term:`tile <Tile>`::
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<...>
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LIOB33.IOB_Y0.IBUFDISABLE.I 38_82
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LIOB33.IOB_Y0.IN_TERM.NONE !38_120 !38_122 !39_121 !39_123
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LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 38_120 38_122 39_121 39_123
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LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 38_120 38_122 !39_121 39_123
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LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 38_120 !38_122 !39_121 39_123
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LIOB33.IOB_Y0.INTERMDISABLE.I 39_89
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LIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127
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LIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93
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LIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93
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LIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93
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LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
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<...>
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For example, the line::
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LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
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means that the feature ``LIOB33.IOB_Y0.PULLTYPE.PULLUP`` will be set by clearing
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bit ``!38_92`` and setting bits ``38_94`` and ``39_93``.
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Generally, the ``<feature>`` name is linked with its functionality.
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For example, ``LIOB33.IOB_Y0.PULLTYPE.PULLUP`` means that in the LIOB33
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:term:`tile <Tile>`,
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in IOB_Y0 site the *pull type* will be set to *PULLUP*.
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This simply means that all pins belonging to this particular IOB
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will be configured with pull-up.
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