mirror of https://github.com/openXC7/prjxray.git
141 lines
4.9 KiB
ReStructuredText
141 lines
4.9 KiB
ReStructuredText
=============
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tilegrid file
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=============
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The ``tilegrid.json`` is a list of all :term:`tiles <Tile>` in the device.
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This information is used at various stages of the flow i.e. for
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:term:`database <Database>` generation or creating a :term:`bitstream <Bitstream>`.
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The most important parts of the file are related to :term:`frame <Frame>` addressing
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within the :term:`bitstream <Bitstream>`, grid and :term:`clock region <Clock region>`
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location, list of underlying :term:`sites <Site>`, or the type of the
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:term:`tile <Tile>` itself.
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Before diving into this section, it is advised to familiarize yourself with the
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7-Series :doc:`Bitstream Format <../../architecture/bitstream_format>` chapter and
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:doc:`Configuration <../../architecture/configuration>` chapter.
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File format
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-----------
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The file consists of the entries describing every :term:`tile <Tile>` in
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the FPGA chip. The file is of the form::
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{
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"<TILE_NAME>": {
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"bits": {
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"<CONFIGURATION_BUS>": {
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"baseaddr": "<BASE_ADDR>,
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"frames": 28,
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"offset": 97,
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"words": 2
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},
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<...>
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},
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"clock_region": <CLOCK_REGION>,
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"grid_x": <GRID_X>,
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"grid_y": <GRID_Y>,
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"pin_functions": {
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"<PIN_NAME">: "<PIN_FUNCTION>",
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<...>
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},
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"prohibited_sites": [
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"<SITE_TYPE>",
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<...>
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],
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"sites": {
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"<SITE_NAME>": <SITE_TYPE>,
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<...>
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},
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"type": "INT_R"
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}
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The ``<TILE_NAME>`` indicates the name of the :term:`tile <Tile>` described
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in the entry. The naming convention matches Vivado.
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Each :term:`tile <Tile>` entry in the file has the following fields:
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- ``"bits"`` - contains the data related to :term:`tile <Tile>` configuration over
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the ``<CONFIGURATION_BUS>``. There are three types of the configuration
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buses in 7-Series FPGAs: ``CLB_IO_CLK``, ``BLOCK_RAM`` and ``CFG_CLB``.
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Every ``<CONFIGURATION_BUS>`` has the following fields:
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- ``baseaddr`` - Basic address of the configuration :term:`frame <Frame>`.
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Every configuration :term:`frame <Frame>` consist of 101 of 32bit
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:term:`words <Word>`. Note that a single :term:`frame <Frame>` usually configures
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a bunch of :term:`tiles <Tile>` connected to the single configuration bus.
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- ``"frames"`` - Number of :term:`frames <Frame>` that can configure the
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:term:`tile <Tile>`.
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- ``offset`` - How many words of offset is present in the :term:`frame <Frame>`
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before the first :term:`word <Word>` that configures the :term:`tile <Tile>`.
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- ``words`` - How many 32bit :term:`words <Word>` configure the :term:`tile <Tile>`.
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- ``clock_region`` - indicates to which :term:`clock region <Clock region>` the
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:term:`tile <Tile>` belongs to.
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- ``grid_x`` - :term:`tile <Tile>` column, increasing right
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- ``grid_y`` - :term:`tile <Tile>` row, increasing down
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- ``pin_functions`` - indicates the special functions of the :term:`tile <Tile>` pins.
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Usually it is related to IOB blocks and indicates i.e. differential output pins.
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- ``prohibited_sites`` - Indicates which :term:`site <Site>` types cannot be used
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in the :term:`tile <Tile>`
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- ``sites`` - dictionary which contains information about the :term:`sites <Site>`
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which can be found inside the :term:`tile <Tile>`. Every entry in
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the dictionary contains the following information:
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- ``"<SITE_NAME>"`` - The unique name of the :term:`site <Site>` inside
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the :term:`tile <Tile>`.
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- ``"<SITE_TYPE>`` - The type of the :term:`site <Site>`
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- ``type`` - The type of the :term:`tile <Tile>`
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Examples
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--------
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.. code-block:: javascript
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"CLBLL_L_X16Y149": {
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"bits": {
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"CLB_IO_CLK": {
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"baseaddr": "0x00020800",
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"frames": 36,
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"offset": 99,
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"words": 2
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}
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},
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"clock_region": "X0Y2",
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"grid_x": 43,
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"grid_y": 1,
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"pin_functions": {},
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"sites": {
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"SLICE_X24Y149": "SLICEL",
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"SLICE_X25Y149": "SLICEL"
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},
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"type": "CLBLL_L"
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}
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Interpreted as:
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- :term:`Tile <Tile>` is named ``CLBLL_L_X16Y149``
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- :term:`Frame <Frame>` base address is ``0x00020800``
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- For each :term:`frame <Frame>`, skip the first 99 words loaded into FDRI
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- Since it's 2 FDRI words out of possible 101, it's the last 2 words
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- It spans across 36 different :term:`frame <Frame>` loads
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- Located in :term:`clock region <Clock region>` ``X0Y2``
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- Located at row 1, column 43
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- Contains two :term:`sites <Site>`, both of which are SLICEL
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- Is a ``CLBLL_L`` type :term:`tile <Tile>`
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More information about :term:`frames <Frame>` and the FPGA configuration can be found in the
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:doc:`Configuration <../../architecture/configuration>` chapter.
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Example of absolute :term:`frame <Frame>` address calculation can be found in the
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:doc:`mask file <../common/mask>` chapter.
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