mirror of https://github.com/openXC7/prjxray.git
29 lines
511 B
Verilog
29 lines
511 B
Verilog
`default_nettype none
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// ============================================================================
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module lfsr #
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(
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parameter WIDTH = 16, // LFSR width
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parameter [WIDTH-1:0] POLY = 16'hD008, // Polynomial
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parameter [WIDTH-1:0] SEED = 1 // Initial value
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)
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(
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input wire clk,
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input wire rst,
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input wire ce,
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output reg [WIDTH-1:0] r
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);
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wire feedback = ^(r & POLY);
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always @(posedge clk) begin
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if(rst) begin
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r <= SEED;
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end else if(ce) begin
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r <= {r[WIDTH-2:0], feedback};
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end
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end
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endmodule
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