mirror of https://github.com/openXC7/prjxray.git
31 lines
513 B
Verilog
31 lines
513 B
Verilog
`default_nettype none
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// ============================================================================
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module lfsr #
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(
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parameter WIDTH = 16, // LFSR width
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parameter [WIDTH-1:0] POLY = 16'hD008, // Polynomial
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parameter [WIDTH-1:0] SEED = 1 // Initial value
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)
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(
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input wire CLK,
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input wire CE,
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input wire RST,
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output reg [WIDTH-1:0] O
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);
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wire feedback = ^(O & POLY);
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always @(posedge CLK) begin
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if(RST) begin
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O <= SEED;
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end else if(CE) begin
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O <= {O[WIDTH-2:0], feedback};
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end
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end
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endmodule
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