mirror of https://github.com/openXC7/prjxray.git
138 lines
3.5 KiB
Python
138 lines
3.5 KiB
Python
#!/usr/bin/env python
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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import sys
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def gen_bram36():
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#yield "RAMB36_X%dY%d" % (x, y)
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMBFIFO36E1']):
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yield site_name
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DUTN = 10
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.csv', 'w')
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f.write('module,loc,pdata,data\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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def randbits(n):
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return ''.join([random.choice(('0', '1')) for _x in range(n)])
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def make(module, gen_locs, pdatan, datan):
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loci = 0
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for loci, loc in enumerate(gen_locs()):
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if loci >= DUTN:
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break
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pdata = randbits(pdatan * 0x100)
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data = randbits(datan * 0x100)
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print(' %s #(' % module)
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for i in range(pdatan):
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print(
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" .INITP_%02X(256'b%s)," %
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(i, pdata[i * 256:(i + 1) * 256]))
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for i in range(datan):
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print(
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" .INIT_%02X(256'b%s)," %
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(i, data[i * 256:(i + 1) * 256]))
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print(' .LOC("%s"))' % (loc, ))
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print(
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' inst_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
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% (loci, 8 * loci, 8 * loci))
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f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
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print('')
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loci += 1
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assert loci == DUTN
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make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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print(
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'''
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module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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''')
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for i in range(16):
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print(
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" parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print('')
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for i in range(0x80):
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print(
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" parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print('')
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print('''\
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(* LOC=LOC *)
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RAMB36E1 #(''')
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for i in range(16):
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print(' .INITP_%02X(INITP_%02X),' % (i, i))
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print('')
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for i in range(0x80):
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print(' .INIT_%02X(INIT_%02X),' % (i, i))
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print('')
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print(
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'''
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.IS_CLKARDCLK_INVERTED(1'b0),
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.IS_CLKBWRCLK_INVERTED(1'b0),
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.IS_ENARDEN_INVERTED(1'b0),
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.IS_ENBWREN_INVERTED(1'b0),
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.IS_RSTRAMARSTRAM_INVERTED(1'b0),
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.IS_RSTRAMB_INVERTED(1'b0),
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.IS_RSTREGARSTREG_INVERTED(1'b0),
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.IS_RSTREGB_INVERTED(1'b0),
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.RAM_MODE("TDP"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST"),
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.SIM_DEVICE("VIRTEX6")
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(dout[1]),
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.DOPADOP(dout[2]),
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.DOPBDOP(dout[3]));
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endmodule
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''')
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