mirror of https://github.com/openXC7/prjxray.git
128 lines
3.5 KiB
Python
128 lines
3.5 KiB
Python
#!/usr/bin/env python
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'''
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Note: vivado will (by default) fail bitgen DRC on LUT feedback loops
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Looks like can probably be disabled, but we actually don't need a bitstream for timing analysis
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ERROR: [Vivado 12-2285] Cannot set LOC property of instance 'roi/lut_x22y102_D', Instance roi/lut_x22y102_D can not be placed in D6LUT of site SLICE_X18Y103 because the bel is occupied by roi/lut_x18y103_D(port:). This could be caused by bel constraint conflict
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Resolution: When using BEL constraints, ensure the BEL constraints are defined before the LOC constraints to avoid conflicts at a given site.
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'''
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import argparse
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import random
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random.seed()
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parser = argparse.ArgumentParser(description='')
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parser.add_argument('--sdx', default='8', help='')
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parser.add_argument('--sdy', default='4', help='')
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args = parser.parse_args()
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'''
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Generate in pairs
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Fill up switchbox quad for now
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Create random connections between the LUTs
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See how much routing pressure we can generate
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Start with non-random connections to the LFSR for solver comparison
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Start at SLICE_X16Y102
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'''
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SBASE = (16, 102)
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SDX = int(args.sdx, 0)
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SDY = int(args.sdy, 0)
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nlut = 4 * SDX * SDY
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nin = 6 * nlut
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nout = nlut
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print('//placelut w/ FF + feedback')
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print('//SBASE: %s' % (SBASE, ))
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print('//SDX: %s' % (SDX, ))
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print('//SDY: %s' % (SDX, ))
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print('//nlut: %s' % (nlut, ))
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print(
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'''\
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module roi (
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input wire clk,
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input wire [%u:0] ins,
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output wire [%u:0] outs);''') % (nin - 1, nout - 1)
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ini = 0
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outi = 0
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for lutx in xrange(SBASE[0], SBASE[0] + SDX):
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for luty in xrange(SBASE[1], SBASE[1] + SDY):
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loc = "SLICE_X%uY%u" % (lutx, luty)
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for belc in 'ABCD':
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bel = '%c6LUT' % belc
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name = 'lut_x%uy%u_%c' % (lutx, luty, belc)
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print(
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'''\
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(* KEEP, DONT_TOUCH, LOC="%s", BEL="%s" *)
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LUT6 #(
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.INIT(64'hBAD1DEA_1DEADCE0)
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) %s (''') % (loc, bel, name)
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for i in xrange(6):
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rval = random.randint(0, 9)
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if rval < 3:
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wfrom = 'ins[%u]' % ini
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ini += 1
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#elif rval < 6:
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# wfrom = 'outsr[%u]' % random.randint(0, nout - 1)
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else:
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wfrom = 'outs[%u]' % random.randint(0, nout - 1)
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print('''\
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.I%u(%s),''' % (i, wfrom))
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out_w = name + '_o'
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print('''\
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.O(%s));''') % (out_w, )
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outs_w = "outs[%u]" % outi
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if random.randint(0, 9) < 5:
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print(' assign %s = %s;' % (outs_w, out_w))
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else:
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out_r = name + '_or'
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print(
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'''\
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reg %s;
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assign %s = %s;
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always @(posedge clk) begin
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%s = %s;
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end
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''' % (out_r, outs_w, out_r, out_r, out_w))
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outi += 1
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#assert nin == ini
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assert nout == outi
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print(
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'''
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endmodule
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module top(input wire clk, input wire stb, input wire di, output wire do);
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localparam integer DIN_N = %u;
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localparam integer DOUT_N = %u;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi(
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.clk(clk),
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.ins(din),
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.outs(dout)
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);
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endmodule''') % (nin, nout)
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