mirror of https://github.com/openXC7/prjxray.git
38 lines
858 B
Verilog
38 lines
858 B
Verilog
module roi (
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input wire clk,
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output wire out);
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reg [23:0] counter;
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assign out = counter[23] ^ counter[22] ^ counter[2] && counter[1] || counter[0];
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always @(posedge clk) begin
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counter <= counter + 1;
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end
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endmodule
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module top(input wire clk, input wire stb, input wire di, output wire do);
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localparam integer DIN_N = 0;
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localparam integer DOUT_N = 1;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi(
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.clk(clk),
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.out(dout[0])
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);
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endmodule
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