mirror of https://github.com/openXC7/prjxray.git
32 lines
640 B
Verilog
32 lines
640 B
Verilog
module top(input clk, din, stb, output dout);
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reg [33:0] din_bits;
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wire [70:0] dout_bits;
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reg [33:0] din_shr;
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reg [70:0] dout_shr;
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always @(posedge clk) begin
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if (stb) begin
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din_bits <= din_shr;
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dout_shr <= dout_bits;
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end else begin
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din_shr <= {din_shr, din};
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dout_shr <= {dout_shr, din_shr[33]};
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end
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end
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assign dout = dout_shr[70];
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picorv32 picorv32 (
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.clk(clk),
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.resetn(din_bits[0]),
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.mem_valid(dout_bits[0]),
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.mem_instr(dout_bits[1]),
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.mem_ready(din_bits[1]),
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.mem_addr(dout_bits[33:2]),
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.mem_wdata(dout_bits[66:34]),
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.mem_wstrb(dout_bits[70:67]),
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.mem_rdata(din_bits[33:2])
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);
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endmodule
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