mirror of https://github.com/openXC7/prjxray.git
90 lines
1.8 KiB
Verilog
90 lines
1.8 KiB
Verilog
`include "src/rom.v"
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`include "src/serializer.v"
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`include "src/transmitter.v"
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`include "src/receiver.v"
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`include "src/comparator.v"
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`include "src/iserdes_sdr_ddr_test.v"
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`default_nettype none
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// ============================================================================
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module top
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(
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input wire clk,
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input wire rx,
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output wire tx,
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input wire [15:0] sw,
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output wire [15:0] led,
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inout wire [9:0] io
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);
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// ============================================================================
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// Clock & reset
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge clk)
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if (sw[0])
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rst_sr <= 4'hF;
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else
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rst_sr <= rst_sr >> 1;
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wire CLK = clk;
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wire RST = rst_sr[0];
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// ============================================================================
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// Test uints
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wire [9:0] error;
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genvar i;
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generate for (i=0; i<10; i=i+1) begin
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localparam DATA_WIDTH = (i == 0) ? 2 :
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(i == 1) ? 3 :
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(i == 2) ? 4 :
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(i == 3) ? 5 :
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(i == 4) ? 6 :
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(i == 5) ? 7 :
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(i == 6) ? 8 :
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(i == 7) ? 4 :
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(i == 8) ? 6 :
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/*(i == 9) ?*/ 8;
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localparam DATA_RATE = (i < 7) ? "SDR" : "DDR";
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iserdes_sdr_ddr_test #
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(
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.DATA_WIDTH (DATA_WIDTH),
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.DATA_RATE (DATA_RATE)
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)
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iserdes_test
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(
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.CLK (CLK),
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.RST (RST),
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.IO_DAT (io[i]),
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.O_ERROR (error[i])
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);
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end endgenerate
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// ============================================================================
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// I/O connections
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reg [23:0] heartbeat_cnt;
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always @(posedge CLK)
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heartbeat_cnt <= heartbeat_cnt + 1;
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assign led[9: 0] = (RST) ? 9'd0 : ~error;
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assign led[ 10] = heartbeat_cnt[22];
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assign led[15:11] = 0;
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endmodule
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