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prjxray/minitests/litex_litedram/src.yosys
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Tomasz Michalak 43fe925ff3 minitests: Add test for Litex DRAM memory interface 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 		2019-10-24 14:28:37 +02:00
..
verilog minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00
ExtractFrames.py minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00
Makefile minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00
mem.init minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00
mem_1.init minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00
synth.ys minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00
top.tcl minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00
top.xdc minitests: Add test for Litex DRAM memory interface 2019-10-24 14:28:37 +02:00