prjxray/minitests/srl/syn.tcl

12 lines
357 B
Tcl

create_project -force -name $env(PROJECT_NAME) -part xc7a35ticsg324-1L
read_verilog ../$env(PROJECT_NAME).v
synth_design -top top
report_timing_summary -file top_timing_synth.rpt
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
report_utilization -file top_utilization_synth.rpt
write_edif -force ../$env(PROJECT_NAME).edif