mirror of https://github.com/openXC7/prjxray.git
157 lines
5.2 KiB
Python
157 lines
5.2 KiB
Python
import os
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import random
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import json
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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def gen_sites():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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for tile in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile)
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gridinfo = grid.gridinfo_at_loc(loc)
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if gridinfo.tile_type in ['DSP_L', 'DSP_R']:
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for site in sorted(gridinfo.sites.keys()):
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if gridinfo.sites[site] == 'DSP48E1':
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yield tile, site
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def fuzz(*args):
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if len(args) == 1 and isinstance(args[0], int):
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# Argument indicates that we should generate a random integer with
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# args[0] number of bits.
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return random.getrandbits(args[0])
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else:
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# Otherwise make a random choice
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return random.choice(*args)
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def run():
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verilog.top_harness(48, 48)
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print('module roi(input clk, input [47:0] din, output [47:0] dout);')
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data = {}
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data['instances'] = []
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sites = list(gen_sites())
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for i, (tile, site) in enumerate(sites):
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synthesis = '(* KEEP, DONT_TOUCH, LOC = "%s" *)' % (site)
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module = 'DSP48E1'
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instance = 'INST_%s' % (site)
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ports = {}
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params = {}
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ports['A'] = '{30{1\'b1}}'
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ports['ACIN'] = '{30{1\'b1}}'
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ports['ACOUT'] = '30\'b0'
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ports['ALUMODE'] = 'din[3:0]'
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ports['B'] = '{18{1\'b1}}'
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ports['BCIN'] = '{18{1\'b1}}'
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ports['BCOUT'] = '18\'b0'
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ports['C'] = '{48{1\'b1}}'
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ports['CARRYCASCIN'] = '1\'b1'
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ports['CARRYCASCOUT'] = '1\'b0'
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ports['CARRYIN'] = 'din[4]'
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ports['CARRYINSEL'] = '3\'b000'
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ports['CARRYOUT'] = '4\'b0'
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ports['CEA1'] = '1\'b1'
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ports['CEA2'] = '1\'b1'
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ports['CEAD'] = '1\'b1'
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ports['CEALUMODE'] = '1\'b1'
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ports['CEB1'] = '1\'b1'
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ports['CEB2'] = '1\'b1'
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ports['CEC'] = '1\'b1'
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ports['CECARRYIN'] = '1\'b1'
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ports['CECTRL'] = '1\'b1'
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ports['CED'] = '1\'b1'
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ports['CEINMODE'] = '1\'b1'
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ports['CEM'] = '1\'b1'
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ports['CEP'] = '1\'b1'
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ports['CLK'] = 'clk'
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ports['D'] = '{25{1\'b1}}'
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ports['INMODE'] = 'din[9:5]'
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#ports['MULTISIGNIN'] = '1\'b1'
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#ports['MULTISIGNOUT'] = '1\'b0'
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ports['OPMODE'] = 'din[16:10]'
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ports['OVERFLOW'] = '1\'b0'
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ports['P'] = '48\'b0'
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ports['PATTERNBDETECT'] = '1\'b0'
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ports['PATTERNDETECT'] = '1\'b0'
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ports['PCIN'] = '{48{1\'b1}}'
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ports['PCOUT'] = '48\'b0'
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ports['RSTA'] = '1\'b1'
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ports['RSTALLCARRYIN'] = '1\'b1'
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ports['RSTALUMODE'] = '1\'b1'
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ports['RSTB'] = '1\'b1'
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ports['RSTC'] = '1\'b1'
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ports['RSTCTRL'] = '1\'b1'
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ports['RSTD'] = '1\'b1'
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ports['RSTINMODE'] = '1\'b1'
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ports['RSTM'] = '1\'b1'
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ports['RSTP'] = '1\'b1'
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ports['UNDERFLOW'] = '1\'b0'
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params['ADREG'] = fuzz((0, 1))
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params['ALUMODEREG'] = fuzz((0, 1))
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params['AREG'] = fuzz((0, 1, 2))
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if params['AREG'] == 0 or params['AREG'] == 1:
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params['ACASCREG'] = params['AREG']
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else:
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params['ACASCREG'] = fuzz((1, 2))
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params['BREG'] = fuzz((0, 1, 2))
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if params['BREG'] == 0 or params['BREG'] == 1:
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params['BCASCREG'] = params['BREG']
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else:
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params['BCASCREG'] = fuzz((1, 2))
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params['CARRYINREG'] = fuzz((0, 1))
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params['CARRYINSELREG'] = fuzz((0, 1))
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params['CREG'] = fuzz((0, 1))
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params['DREG'] = fuzz((0, 1))
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params['INMODEREG'] = fuzz((0, 1))
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params['OPMODEREG'] = fuzz((0, 1))
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params['PREG'] = fuzz((0, 1))
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params['A_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
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params['B_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
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params['USE_DPORT'] = verilog.quote(fuzz(('TRUE', 'FALSE')))
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params['USE_SIMD'] = verilog.quote(fuzz(('ONE48', 'TWO24', 'FOUR12')))
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params['USE_MULT'] = verilog.quote(
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'NONE' if params['USE_SIMD'] != verilog.quote('ONE48') else fuzz(
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('NONE', 'MULTIPLY', 'DYNAMIC')))
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params['MREG'] = 0 if params['USE_MULT'] == verilog.quote(
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'NONE') else fuzz((0, 1))
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params['AUTORESET_PATDET'] = verilog.quote(
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fuzz(('NO_RESET', 'RESET_MATCH', 'RESET_NOT_MATCH')))
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params['MASK'] = '48\'d%s' % fuzz(48)
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params['PATTERN'] = '48\'d%s' % fuzz(48)
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params['SEL_MASK'] = verilog.quote(
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fuzz(('MASK', 'C', 'ROUNDING_MODE1', 'ROUNDING_MODE2')))
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params['USE_PATTERN_DETECT'] = verilog.quote(
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fuzz(('NO_PATDET', 'PATDET')))
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params['IS_ALUMODE_INVERTED'] = fuzz(4)
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params['IS_CARRYIN_INVERTED'] = fuzz((0, 1))
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params['IS_CLK_INVERTED'] = fuzz((0, 1))
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params['IS_INMODE_INVERTED'] = fuzz(5)
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params['IS_OPMODE_INVERTED'] = fuzz(7)
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verilog.instance(synthesis + ' ' + module, instance, ports, params)
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params['TILE'] = tile
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params['SITE'] = site
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data['instances'].append(params)
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with open('params.json', 'w') as fp:
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json.dump(data, fp)
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print("endmodule")
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if __name__ == '__main__':
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run()
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