mirror of https://github.com/openXC7/prjxray.git
83 lines
3.1 KiB
Makefile
83 lines
3.1 KiB
Makefile
# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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SHELL = bash
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SYNTH ?= vivado
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YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
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PART = xc7a200tsbg484-1
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PROJECT_NAME = display_port
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all: $(PROJECT_NAME).fasm
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clean:
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@rm -rf build*
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@rm -f *.edif
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@rm -f *.bit
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@rm -f *.bin
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@rm -f *.log
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@rm -f *.dcp
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@rm -f *.fasm
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help:
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@echo "Usage: make all [SYNTH=<vivado/yosys>]"
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.PHONY: clean help
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$(YOSYS):
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cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
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DISPLAY_PORT_DIR = $(XRAY_DIR)/third_party/display_port
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VERILOG_FILES = $(DISPLAY_PORT_DIR)/src/test_streams/test_source.v \
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$(DISPLAY_PORT_DIR)/src/debug/seven_segment_driver.v \
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$(DISPLAY_PORT_DIR)/src/test_streams/insert_main_stream_attrbutes_four_channels.v \
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$(DISPLAY_PORT_DIR)/src/test_streams/test_source_3840_2180_YCC_422_ch2.v \
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$(DISPLAY_PORT_DIR)/src/insert_training_pattern.v \
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$(DISPLAY_PORT_DIR)/src/main_stream_processing.v \
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$(DISPLAY_PORT_DIR)/src/auxch/channel_managemnt.v \
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$(DISPLAY_PORT_DIR)/src/auxch/hotplug_decode.v \
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$(DISPLAY_PORT_DIR)/src/auxch/dp_register_decode.v \
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$(DISPLAY_PORT_DIR)/src/skew_channels.v \
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$(DISPLAY_PORT_DIR)/src/test_streams/insert_main_stream_attrbutes_two_channels.v \
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$(DISPLAY_PORT_DIR)/src/auxch/aux_channel.v \
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$(DISPLAY_PORT_DIR)/src/auxch/dp_aux_messages.v \
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$(DISPLAY_PORT_DIR)/src/auxch/aux_interface.v \
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$(DISPLAY_PORT_DIR)/src/test_streams/insert_main_stream_attrbutes_one_channel.v \
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$(DISPLAY_PORT_DIR)/src/artix7/transceiver.v \
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$(DISPLAY_PORT_DIR)/src/scrambler_reset_inserter.v \
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$(DISPLAY_PORT_DIR)/src/artix7/gtx_tx_reset_controller.v \
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$(DISPLAY_PORT_DIR)/src/idle_pattern_inserter.v \
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$(DISPLAY_PORT_DIR)/src/artix7/transceiver_bank.v \
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$(DISPLAY_PORT_DIR)/src/auxch/link_signal_mgmt.v \
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$(DISPLAY_PORT_DIR)/src/auxch/edid_decode.v \
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$(DISPLAY_PORT_DIR)/src/scrambler_all_channels.v \
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$(DISPLAY_PORT_DIR)/src/top_level_nexys_video.v
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CONSTRAINT_FILES = $(DISPLAY_PORT_DIR)/constraints/NexysVideo.xdc
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ifeq ($(SYNTH), yosys)
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$(PROJECT_NAME).edif: $(YOSYS)
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$(YOSYS) -p "read_verilog $(VERILOG_FILES); synth_xilinx -arch xc7 -flatten -nosrl -nodsp -top top_level_nexys_video; write_edif -pvector bra -attrprop $@" -l $@.log
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else ifeq ($(SYNTH), vivado)
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$(PROJECT_NAME).edif: tcl/syn.tcl
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mkdir -p build-syn.$(basename $@)
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cd build-syn.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) VERILOG_FILES="$(VERILOG_FILES)" $(XRAY_VIVADO) -mode batch -source ../tcl/syn.tcl -nojournal -log ../$@.log
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rm -rf *.backup.log
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endif
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$(PROJECT_NAME).bit: $(PROJECT_NAME).edif tcl/par.tcl
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mkdir -p build-par.$(basename $@)
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cd build-par.$(basename $@) && env PART=$(PART) PROJECT_NAME=$(PROJECT_NAME) CONSTRAINT_FILES=$(CONSTRAINT_FILES) $(XRAY_VIVADO) -mode batch -source ../tcl/par.tcl -nojournal -log ../$@.log
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rm -rf *.backup.log
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$(PROJECT_NAME).fasm: $(PROJECT_NAME).bit
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source $(XRAY_DIR)/settings/artix7_200t.sh && env XRAY_PART=$(PART) ${XRAY_BIT2FASM} --verbose $(PROJECT_NAME).bit > $(PROJECT_NAME).fasm
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