mirror of https://github.com/openXC7/prjxray.git
308 lines
6.0 KiB
Plaintext
308 lines
6.0 KiB
Plaintext
meta:
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id: xilinx_bitstream
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title: Xilinx FPGA Bitstream
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license: Apache-2.0
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endian: be
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seq:
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- id: padding
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terminator: 0xaa
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- id: magic
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contents: [0x99, 0x55, 0x66]
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- id: contents
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type: packet
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repeat: eos
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types:
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packet:
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seq:
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- id: header
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size: 4
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type: header
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- id: data
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if: header.opcode != opcode::nop
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size: header.word_count * 4
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type:
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switch-on: header.register_address
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cases:
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register::crc: reg_crc
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register::timer: reg_timer
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register::wbstar: reg_wbstar
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register::cmd: reg_cmd
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register::cor0: reg_cor0
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register::cor1: reg_cor1
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register::idcode: reg_idcode
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register::mask: reg_mask
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register::ctl0: reg_ctl0
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register::ctl1: reg_ctl1
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register::far: reg_far
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register::fdri: reg_fdri
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header:
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seq:
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- id: type
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type: b3
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- id: opcode
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type: b2
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enum: opcode
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- id: register_address
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type: b14
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enum: register
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if: type == 0x1
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- id: reserved
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type: b2
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if: type == 0x1
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- id: word_count
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type: b11
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if: type == 0x1
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- id: word_count
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type: b27
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if: type == 0x2
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reg_crc:
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seq:
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- id: expected_crc
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type: u4
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reg_timer:
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seq:
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- id: timer_usr_mon
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type: b1
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enum: enable
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- id: timer_cfg_mon
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type: b1
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enum: enable
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- id: timer_value
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type: b30
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reg_wbstar:
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seq:
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- id: rs
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type: b2
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doc: 'RS[1:0] pin value on next warm boot.'
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- id: rs_ts_b
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type: b1
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doc: 'Whether RS[1:0] are tristated on next warm boot.'
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enum: tristate_enable
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- id: start_address
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type: b29
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doc: 'Address of bitstream to start on next warm boot.'
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reg_cmd:
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seq:
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- id: command
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type: u4
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enum: command
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reg_cor0:
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seq:
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- id: pwrdwn_stat
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type: b1
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enum: cor0_pwrdwn_stat
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- id: done_pipe
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type: b1
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doc: 'When set, adds a register between DONEIN and any configuration logic'
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- id: drive_done
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type: b1
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enum: cor0_drive_done
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- id: single
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type: b1
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doc: 'When set, readback is a single-shot operation and must be reset by loading RCAP into CMD.'
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- id: oscfsel
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type: b6
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doc: 'CCLK frequency in MHz when in Master modes'
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- id: ssclksrc
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type: b2
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enum: cor0_ssclksrc
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- id: done_cycle
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type: b3
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enum: cor0_startup_phase
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- id: match_cycle
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type: b3
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enum: cor0_startup_phase_no_wait
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- id: lock_cycle
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type: b3
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enum: cor0_startup_phase_no_wait
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- id: gts_cycle
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type: b3
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enum: cor0_startup_phase
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- id: gwe_cycle
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type: b3
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enum: cor0_startup_phase
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reg_cor1:
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seq:
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- id: reserved
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type: u4
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reg_idcode:
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seq:
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- id: idcode
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type: u4
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reg_mask:
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seq:
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- id: mask
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type: u4
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reg_ctl0:
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seq:
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- id: efuse_key
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type: b1
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enum: ctl0_efuse_key
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- id: icap_select
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type: b1
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enum: ctl0_icap_select
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- id: reserved1
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type: b17
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- id: overtemp_power_down
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type: b1
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enum: enable
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- id: reserved2
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type: b1
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- id: config_fallback
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enum: disable
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type: b1
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- id: reserved3
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type: b1
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- id: glutmask_b
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type: b1
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enum: ctl0_glutmask_b
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- id: farsrc
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type: b1
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enum: ctl0_farsrc
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- id: dec
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type: b1
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enum: enable
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- id: sbits
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type: b2
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enum: ctl0_sbits
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- id: persist
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type: b1
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enum: enable
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- id: gts_usr_b
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type: b1
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enum: tristate_enable
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reg_ctl1:
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seq:
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- id: reserved
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type: u4
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reg_far:
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seq:
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- id: reserved
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type: b7
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- id: block_type
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type: b2
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enum: far_block_type
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- id: is_bottom_half_rows
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type: b1
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- id: row_address
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type: b5
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- id: column_address
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type: b10
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- id: minor_address
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type: b7
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reg_fdri:
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seq:
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- id: frames
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type: frame
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repeat: eos
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frame:
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seq:
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- id: config_word
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type: u4
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repeat: expr
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repeat-expr: 101
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enums:
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opcode:
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0: nop
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1: read
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2: write
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3: reserved
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register:
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0: crc
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1: far
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2: fdri
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3: fdro
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4: cmd
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5: ctl0
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6: mask
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7: stat
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8: lout
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9: cor0
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10: mfwr
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11: cbc
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12: idcode
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13: axxs
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14: cor1
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16: wbstar
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17: timer
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22: bootsts
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24: ctl1
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31: bspi
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enable:
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0: disabled
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1: enabled
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disable:
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0: enabled
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1: disabled
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tristate_enable:
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0: tristate
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1: driven
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command:
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0: 'null'
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1: wcfg
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2: mfw
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3: dghigh_lfrm
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4: rcfg
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5: start
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6: rcap
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7: rcrc
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8: aghigh
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9: switch
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10: grestore
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11: shutdown
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12: gcapture
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13: desync
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15: iprog
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16: crcc
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17: ltimer
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18: bspi_read
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19: fall_edge
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cor0_pwrdwn_stat:
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0: done_pin
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1: powerdown_pin
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cor0_startup_phase_no_wait:
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0: startup_phase_0
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1: startup_phase_1
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2: startup_phase_2
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3: startup_phase_3
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4: startup_phase_4
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5: startup_phase_5
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6: startup_phase_6
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7: no_wait
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cor0_startup_phase:
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0: startup_phase_1
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1: startup_phase_2
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2: startup_phase_3
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3: startup_phase_4
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4: startup_phase_5
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5: startup_phase_6
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6: track_done
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7: keep
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cor0_ssclksrc:
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0: cclk
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1: userclk
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2: jtagclk
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3: jtagclk
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cor0_drive_done:
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0: open_drain
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1: drive_high
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ctl0_efuse_key:
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0: battery_backed_ram
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1: efuse
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ctl0_icap_select:
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0: top
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1: bottom
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ctl0_glutmask_b:
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0: exclude_memory_cells_in_readback
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1: include_memory_cells_in_readback
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ctl0_farsrc:
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0: efar
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1: far
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ctl0_sbits:
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0: read_write
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1: write_only
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2: none
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far_block_type:
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0: clb_io_clk
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1: block_ram
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2: cfg_clb |