mirror of https://github.com/openXC7/prjxray.git
961 lines
24 KiB
Verilog
961 lines
24 KiB
Verilog
/*
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SLICEM at the following:
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SLICE_XxY*
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Where Y any value
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x
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Always even (ie 100, 102, 104, etc)
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In our ROI
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x = 6, 8, 10, 12, 14
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SRL16E: LOC + BEL
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SRLC32E: LOC + BEL
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RAM64X1S: LOCs but doesn't BEL (or maybe I'm using the wrong BEL?)
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*/
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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/*
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Using UG474 recommended primitives
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*/
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module roi(input clk, input [255:0] din, output [255:0] dout);
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my_RAM32X1S #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_RAM32X1D #(.LOC("SLICE_X12Y101"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_RAM32M #(.LOC("SLICE_X12Y102"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X12Y103"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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my_RAM64X1D #(.LOC("SLICE_X12Y104"))
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c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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my_RAM64M #(.LOC("SLICE_X12Y105"))
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c5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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my_RAM128X1S #(.LOC("SLICE_X12Y106"))
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c6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
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my_RAM128X1D #(.LOC("SLICE_X12Y107"))
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c7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
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my_RAM256X1S #(.LOC("SLICE_X12Y108"))
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c8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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//Multi-packing
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my_RAM32X1S_2 #(.LOC("SLICE_X12Y110"))
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m0(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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my_RAM32X1S_3 #(.LOC("SLICE_X12Y111"))
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m1(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
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my_RAM32X1S_4 #(.LOC("SLICE_X12Y112"))
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m2(.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 88 +: 8]));
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my_RAM64X1D_2 #(.LOC("SLICE_X12Y113"))
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m3(.clk(clk), .din(din[ 96 +: 8]), .dout(dout[ 96 +: 8]));
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//next round
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my_RAM64X1S_2 #(.LOC("SLICE_X12Y114"))
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m4(.clk(clk), .din(din[ 104 +: 8]), .dout(dout[ 104 +: 8]));
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my_RAM64X1S_3 #(.LOC("SLICE_X12Y115"))
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m5(.clk(clk), .din(din[ 112 +: 8]), .dout(dout[ 112 +: 8]));
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my_RAM64X1S_4 #(.LOC("SLICE_X12Y116"))
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m6(.clk(clk), .din(din[ 120 +: 8]), .dout(dout[ 120 +: 8]));
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//...and out of bits
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my_RAM128X1S_2 #(.LOC("SLICE_X12Y117"))
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m7(.clk(clk), .din(din[ 200 +: 8]), .dout(dout[ 200 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y100"), .BEL("A6LUT"))
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s0(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y101"), .BEL("B6LUT"))
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s1(.clk(clk), .din(din[ 136 +: 8]), .dout(dout[ 136 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y102"), .BEL("C6LUT"))
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s2(.clk(clk), .din(din[ 144 +: 8]), .dout(dout[ 144 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y103"), .BEL("D6LUT"))
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s3(.clk(clk), .din(din[ 152 +: 8]), .dout(dout[ 152 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y104"), .BEL("A6LUT"))
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s4(.clk(clk), .din(din[ 160 +: 8]), .dout(dout[ 160 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y105"), .BEL("B6LUT"))
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s5(.clk(clk), .din(din[ 168 +: 8]), .dout(dout[ 168 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y106"), .BEL("C6LUT"))
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s6(.clk(clk), .din(din[ 176 +: 8]), .dout(dout[ 176 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y107"), .BEL("D6LUT"))
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s7(.clk(clk), .din(din[ 184 +: 8]), .dout(dout[ 184 +: 8]));
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//my_SRL16E_8 #(.LOC("SLICE_X14Y108"))
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// s8(.clk(clk), .din(din[ 192 +: 8]), .dout(dout[ 192 +: 8]));
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endmodule
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//It created a LUT instead of aggregating using WA7MUX
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module my_RAM64X1S_2_mux (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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assign dout[0] = din[0] ? oa : ob;
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM64X1S #(
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) ramb (
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.O(ob),
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.A0(din[0]),
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.A1(din[0]),
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.A2(din[0]),
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.A3(din[0]),
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.A4(din[0]),
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.A5(din[0]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM64X1S #(
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) rama (
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.O(oa),
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.A0(din[0]),
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.A1(din[0]),
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.A2(din[0]),
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.A3(din[0]),
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.A4(din[0]),
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.A5(din[0]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_SRL16E_4 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, BEL="D6LUT" *)
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SRL16E #(
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) lutd (
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.Q(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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(* LOC=LOC, BEL="C6LUT" *)
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SRL16E #(
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) lutc (
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.Q(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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(* LOC=LOC, BEL="B6LUT" *)
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SRL16E #(
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) lutb (
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.Q(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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(* LOC=LOC, BEL="A6LUT" *)
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SRL16E #(
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) luta (
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.Q(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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endmodule
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module my_SRL16E_8 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, BEL="D6LUT" *)
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SRL16E #(
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) lutd2 (
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.Q(dout[7]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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(* LOC=LOC, BEL="D6LUT" *)
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SRL16E #(
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) lutd1 (
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.Q(dout[6]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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endmodule
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module my_SRLC32E_4 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[3]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[2]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[1]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[0]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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endmodule
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module my_RAM32X1S_2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM32X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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endmodule
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module my_RAM32X1S_3 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM32X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutb (
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.O(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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endmodule
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module my_RAM32X1S_4 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM32X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutb (
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.O(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) luta (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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endmodule
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module my_RAM64X1S_2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
|
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.A2(din[2]),
|
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.A3(din[3]),
|
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.A4(din[4]),
|
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.A5(din[5]),
|
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC *)
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RAM64X1S #(
|
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
|
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.A2(din[2]),
|
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.A3(din[3]),
|
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.A4(din[4]),
|
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.A5(din[5]),
|
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.D(din[6]),
|
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_RAM64X1S_3 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1S #(
|
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) lutd (
|
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.O(dout[3]),
|
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.A0(din[0]),
|
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.A1(din[1]),
|
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.A2(din[2]),
|
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.A3(din[3]),
|
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.A4(din[4]),
|
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.A5(din[5]),
|
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.D(din[6]),
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.WCLK(clk),
|
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.WE(din[0]));
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|
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(* LOC=LOC *)
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RAM64X1S #(
|
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) lutc (
|
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.O(dout[2]),
|
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.A0(din[0]),
|
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.A1(din[1]),
|
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.A2(din[2]),
|
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.A3(din[3]),
|
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.A4(din[4]),
|
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.A5(din[5]),
|
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.D(din[6]),
|
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.WCLK(clk),
|
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.WE(din[0]));
|
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|
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(* LOC=LOC *)
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RAM64X1S #(
|
|
) lutb (
|
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.O(dout[1]),
|
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.A0(din[0]),
|
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.A1(din[1]),
|
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.A2(din[2]),
|
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.A3(din[3]),
|
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.A4(din[4]),
|
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.A5(din[5]),
|
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.D(din[6]),
|
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.WCLK(clk),
|
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.WE(din[0]));
|
|
endmodule
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|
|
module my_RAM64X1S_4 (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC *)
|
|
RAM64X1S #(
|
|
) lutd (
|
|
.O(dout[3]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.D(din[6]),
|
|
.WCLK(clk),
|
|
.WE(din[0]));
|
|
|
|
(* LOC=LOC *)
|
|
RAM64X1S #(
|
|
) lutc (
|
|
.O(dout[2]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.D(din[6]),
|
|
.WCLK(clk),
|
|
.WE(din[0]));
|
|
|
|
(* LOC=LOC *)
|
|
RAM64X1S #(
|
|
) lutb (
|
|
.O(dout[1]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.D(din[6]),
|
|
.WCLK(clk),
|
|
.WE(din[0]));
|
|
|
|
(* LOC=LOC *)
|
|
RAM64X1S #(
|
|
) luta (
|
|
.O(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.D(din[6]),
|
|
.WCLK(clk),
|
|
.WE(din[0]));
|
|
endmodule
|
|
|
|
module my_RAM64X1D_2 (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM64X1D #(
|
|
.INIT(64'h0),
|
|
.IS_WCLK_INVERTED(1'b0)
|
|
) ramb (
|
|
.DPO(dout[1]),
|
|
.D(din[0]),
|
|
.WCLK(clk),
|
|
.WE(din[2]),
|
|
.A0(din[3]),
|
|
.A1(din[4]),
|
|
.A2(din[5]),
|
|
.A3(din[6]),
|
|
.A4(din[7]),
|
|
.A5(din[0]),
|
|
.DPRA0(din[1]),
|
|
.DPRA1(din[2]),
|
|
.DPRA2(din[3]),
|
|
.DPRA3(din[4]),
|
|
.DPRA4(din[5]),
|
|
.DPRA5(din[6]));
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM64X1D #(
|
|
.INIT(64'h0),
|
|
.IS_WCLK_INVERTED(1'b0)
|
|
) rama (
|
|
.DPO(dout[0]),
|
|
.D(din[0]),
|
|
.WCLK(clk),
|
|
.WE(din[2]),
|
|
.A0(din[3]),
|
|
.A1(din[4]),
|
|
.A2(din[5]),
|
|
.A3(din[6]),
|
|
.A4(din[7]),
|
|
.A5(din[0]),
|
|
.DPRA0(din[1]),
|
|
.DPRA1(din[2]),
|
|
.DPRA2(din[3]),
|
|
.DPRA3(din[4]),
|
|
.DPRA4(din[5]),
|
|
.DPRA5(din[6]));
|
|
endmodule
|
|
|
|
//BEL: yes
|
|
module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
parameter BEL="A6LUT";
|
|
|
|
wire mc31c;
|
|
|
|
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
|
SRLC32E #(
|
|
.INIT(32'h00000000),
|
|
.IS_CLK_INVERTED(1'b0)
|
|
) lut (
|
|
.Q(dout[0]),
|
|
.Q31(mc31c),
|
|
.A(din[4:0]),
|
|
.CE(din[5]),
|
|
.CLK(din[6]),
|
|
.D(din[7]));
|
|
endmodule
|
|
|
|
|
|
//BEL: yes
|
|
module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
parameter BEL="A6LUT";
|
|
|
|
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
|
SRL16E #(
|
|
) SRL16E (
|
|
.Q(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.CE(din[4]),
|
|
.CLK(din[5]),
|
|
.D(din[6]));
|
|
endmodule
|
|
|
|
module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
parameter BEL="A6LUT";
|
|
|
|
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
|
RAM64M #(
|
|
) RAM64M (
|
|
.DOA(dout[0]),
|
|
.DOB(dout[1]),
|
|
.DOC(dout[2]),
|
|
.DOD(dout[3]),
|
|
.ADDRA(din[0]),
|
|
.ADDRB(din[1]),
|
|
.ADDRC(din[2]),
|
|
.ADDRD(din[3]),
|
|
.DIA(din[4]),
|
|
.DIB(din[5]),
|
|
.DIC(din[6]),
|
|
.DID(din[7]),
|
|
.WCLK(clk),
|
|
.WE(din[1]));
|
|
endmodule
|
|
|
|
//Can't get BEL to work. Maybe can't since multiple?
|
|
module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
parameter BEL="A6LUT";
|
|
|
|
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
|
RAM64X1S #(
|
|
) RAM64X1S (
|
|
.O(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.D(din[6]),
|
|
.WCLK(clk),
|
|
.WE(din[0]));
|
|
endmodule
|
|
|
|
module my_RAM64X1S_1 (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
parameter BEL="A6LUT";
|
|
|
|
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
|
RAM64X1S_1 #(
|
|
) RAM64X1S_1 (
|
|
.O(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.D(din[6]),
|
|
.WCLK(clk),
|
|
.WE(din[0]));
|
|
endmodule
|
|
|
|
module my_RAM64X2S (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM64X2S #(
|
|
) RAM64X2S (
|
|
.O0(dout[0]),
|
|
.O1(dout[1]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.D0(din[6]),
|
|
.D1(din[7]),
|
|
.WCLK(clk),
|
|
.WE(din[1]));
|
|
endmodule
|
|
|
|
module my_RAM64X1D (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM64X1D #(
|
|
.INIT(64'h0),
|
|
.IS_WCLK_INVERTED(1'b0)
|
|
) RAM64X1D (
|
|
.DPO(dout[0]),
|
|
.D(din[0]),
|
|
.WCLK(clk),
|
|
.WE(din[2]),
|
|
.A0(din[3]),
|
|
.A1(din[4]),
|
|
.A2(din[5]),
|
|
.A3(din[6]),
|
|
.A4(din[7]),
|
|
.A5(din[0]),
|
|
.DPRA0(din[1]),
|
|
.DPRA1(din[2]),
|
|
.DPRA2(din[3]),
|
|
.DPRA3(din[4]),
|
|
.DPRA4(din[5]),
|
|
.DPRA5(din[6]));
|
|
endmodule
|
|
|
|
module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM128X1D #(
|
|
.INIT(128'h0),
|
|
.IS_WCLK_INVERTED(1'b0)
|
|
) RAM128X1D (
|
|
.DPO(dout[0]),
|
|
.SPO(dout[1]),
|
|
.D(din[0]),
|
|
.WCLK(clk),
|
|
.WE(din[2]));
|
|
endmodule
|
|
|
|
module my_RAM128X1S (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM128X1S #(
|
|
) RAM128X1S (
|
|
.O(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.A6(din[6]),
|
|
.D(din[7]),
|
|
.WCLK(din[0]),
|
|
.WE(din[1]));
|
|
endmodule
|
|
|
|
module my_RAM128X1S_2 (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM128X1S #(
|
|
) lutb (
|
|
.O(dout[1]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.A6(din[6]),
|
|
.D(din[7]),
|
|
.WCLK(din[0]),
|
|
.WE(din[1]));
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM128X1S #(
|
|
) luta (
|
|
.O(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.A5(din[5]),
|
|
.A6(din[6]),
|
|
.D(din[7]),
|
|
.WCLK(din[0]),
|
|
.WE(din[1]));
|
|
endmodule
|
|
|
|
module my_RAM256X1S (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM256X1S #(
|
|
) RAM256X1S (
|
|
.O(dout[0]),
|
|
.A({din[0], din[7:0]}),
|
|
.D(din[0]),
|
|
.WCLK(din[1]),
|
|
.WE(din[2]));
|
|
endmodule
|
|
|
|
module my_RAM32M (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM32M #(
|
|
) RAM32M (
|
|
.DOA(dout[1:0]),
|
|
.DOB(dout[3:2]),
|
|
.DOC(dout[5:4]),
|
|
.DOD(dout[7:6]),
|
|
.ADDRA(din[4:0]),
|
|
.ADDRB(din[4:0]),
|
|
.ADDRC(din[4:0]),
|
|
.ADDRD(din[4:0]),
|
|
.DIA(din[5:4]),
|
|
.DIB(din[6:5]),
|
|
.DIC(din[7:6]),
|
|
.DID(din[1:0]),
|
|
.WCLK(din[1]),
|
|
.WE(din[2]));
|
|
endmodule
|
|
|
|
module my_RAM32X1D (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM32X1D #(
|
|
) RAM32X1D (
|
|
.DPO(dout[0]),
|
|
.SPO(dout[1]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.D(din[5]),
|
|
.DPRA0(din[6]),
|
|
.DPRA1(din[7]),
|
|
.DPRA2(din[0]),
|
|
.DPRA3(din[1]),
|
|
.DPRA4(din[2]),
|
|
.WCLK(din[3]),
|
|
.WE(din[4]));
|
|
endmodule
|
|
|
|
/*
|
|
Invalid
|
|
It tries to place both at D6LUT
|
|
module my_RAM32X1D_2 (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM32X1D #(
|
|
) lutb (
|
|
.DPO(dout[3]),
|
|
.SPO(dout[2]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.D(din[5]),
|
|
.DPRA0(din[6]),
|
|
.DPRA1(din[7]),
|
|
.DPRA2(din[0]),
|
|
.DPRA3(din[1]),
|
|
.DPRA4(din[2]),
|
|
.WCLK(din[3]),
|
|
.WE(din[4]));
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM32X1D #(
|
|
) luta (
|
|
.DPO(dout[1]),
|
|
.SPO(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.D(din[5]),
|
|
.DPRA0(din[6]),
|
|
.DPRA1(din[7]),
|
|
.DPRA2(din[0]),
|
|
.DPRA3(din[1]),
|
|
.DPRA4(din[2]),
|
|
.WCLK(din[3]),
|
|
.WE(din[4]));
|
|
endmodule
|
|
*/
|
|
|
|
module my_RAM32X1S (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
parameter BEL="A6LUT";
|
|
|
|
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
|
RAM32X1S #(
|
|
) RAM32X1S (
|
|
.O(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.D(din[5]),
|
|
.WCLK(din[6]),
|
|
.WE(din[7]));
|
|
endmodule
|
|
|
|
module my_RAM32X1S_1 (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
parameter BEL="A6LUT";
|
|
|
|
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
|
RAM32X1S_1 #(
|
|
) RAM32X1S_1 (
|
|
.O(dout[0]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.D(din[5]),
|
|
.WCLK(din[6]),
|
|
.WE(din[7]));
|
|
endmodule
|
|
|
|
module my_RAM32X2S (input clk, input [7:0] din, output [7:0] dout);
|
|
parameter LOC = "";
|
|
|
|
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
|
RAM32X2S #(
|
|
) RAM32X2S (
|
|
.O0(dout[0]),
|
|
.O1(dout[1]),
|
|
.A0(din[0]),
|
|
.A1(din[1]),
|
|
.A2(din[2]),
|
|
.A3(din[3]),
|
|
.A4(din[4]),
|
|
.D0(din[5]),
|
|
.D1(din[6]),
|
|
.WCLK(din[7]),
|
|
.WE(din[0]));
|
|
endmodule
|
|
|