Tim Callahan d9ad4a74da Sort ignored wires for xc7a100t part. ... Signed-off-by: Tim Callahan <tcal@google.com>		2020-04-28 16:00:04 -07:00
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ignored_wires	Sort ignored wires for xc7a100t part.	2020-04-28 16:00:04 -07:00
Makefile	Don't clobber other parts build directories on run target.	2020-02-19 16:34:11 -08:00
analyze_errors.py	Add option to output ignored wires and add ignored wires for kintex7.	2018-11-06 08:32:18 -08:00
cleanup_site_pins.py	Remove xjson from 074.	2020-02-12 14:43:15 -08:00
create_node_tree.py	Remove xjson from 074.	2020-02-12 14:43:15 -08:00
generate.sh	Fuzzer 074 Multi Thread optimisation	2019-01-18 09:17:17 +01:00
generate_after_dump.sh	Attempt to parallelize 074 for additional parts.	2020-02-19 16:34:11 -08:00
generate_grid.py	Some more fixes around ignored tiles within a grid.	2020-02-20 11:33:12 -08:00
generate_ignore_list.py	Run make format.	2018-09-27 08:53:39 -07:00
get_nodescount.tcl	Fuzzer 074 Multi Thread optimisation	2019-01-18 09:17:17 +01:00
get_speed_model.tcl	Fix remap on new 074 code.	2020-02-21 13:01:30 -08:00
get_tilescount.tcl	Fuzzer 074 Multi Thread optimisation	2019-01-18 09:17:17 +01:00
jobnodes.tcl	run make format	2020-01-24 10:13:33 +01:00
jobtiles.tcl	Some more fixes around ignored tiles within a grid.	2020-02-20 11:33:12 -08:00
reduce_site_types.py	Remove xjson from 074.	2020-02-12 14:43:15 -08:00
reduce_tile_types.py	074-dump_all: fix bug when annotating wires speed model	2020-02-19 16:33:32 -08:00
run_fuzzer.py	Remove temp files after 074 completes.	2020-02-19 16:33:32 -08:00