mirror of https://github.com/openXC7/prjxray.git
61 lines
2.2 KiB
Tcl
61 lines
2.2 KiB
Tcl
proc write_iobuf_report {filename} {
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set fp [open $filename w]
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puts $fp "{ \"tiles\": \["
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foreach port [get_ports] {
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set net [get_nets -of $port]
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if { $net == "" } {
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continue
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}
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set cell [get_cells -of $net]
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set site [get_sites -of $cell]
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set tile [get_tiles -of $site]
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puts $fp "{"
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puts $fp "\"port\": \"$port\","
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puts $fp "\"pad_wire\": \"$net\","
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puts $fp "\"cell\": \"$cell\","
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puts $fp "\"site\": \"$site\","
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puts $fp "\"tile\": \"$tile\","
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puts $fp "\"type\": \"[get_property REF_NAME $cell]\","
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puts $fp "\"IOSTANDARD\": \"\\\"[get_property IOSTANDARD $cell]\\\"\","
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puts $fp "\"PULLTYPE\": \"\\\"[get_property PULLTYPE $cell]\\\"\","
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puts $fp "\"DRIVE\": \"[get_property DRIVE $cell]\","
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puts $fp "\"SLEW\": \"\\\"[get_property SLEW $cell]\\\"\","
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puts $fp "},"
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}
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puts $fp "\]}"
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close $fp
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}
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create_project -force -name top -part xc7a35ticsg324-1L
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read_xdc ../top.xdc
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read_edif ../top.edif
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link_design -top top -part xc7a35ticsg324-1L
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report_timing_summary -file top_timing_synth.rpt
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report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
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report_utilization -file top_utilization_synth.rpt
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opt_design
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place_design
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report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
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report_utilization -file top_utilization_place.rpt
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report_io -file top_io.rpt
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report_control_sets -verbose -file top_control_sets.rpt
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report_clock_utilization -file top_clock_utilization.rpt
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route_design
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phys_opt_design
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force top_route.dcp
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report_route_status -file top_route_status.rpt
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report_drc -file top_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
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report_power -file top_power.rpt
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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write_bitstream -force top.bit
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write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
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write_iobuf_report iobuf_report.json5
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quit
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