mirror of https://github.com/openXC7/prjxray.git
586 lines
16 KiB
Python
586 lines
16 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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""" Route timing delay definitions.
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Routing delay is formed from two parts in this model:
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- Intristic delay of the element
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- Capactive loading delay of the net
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Intristic delay is a time value (e.g. nanoseconds), does not vary based on
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routing fanout. It does vary based on the PVT (process, voltage, temperature)
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corner. PvtCorner and IntristicDelay objects are used to model intristic
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delay of elements.
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Capactive loading is the elmore delay from the RC tree formed by interconnect.
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The RC tree is made up of 5 types of RC nodes:
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|Element type |Object |Intrinsic delays?|Output resistance?|Capacitance type |
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|----------------------|--------------|-----------------|------------------|--------------------|
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|Site output pin |Outpin |Yes |Yes |N/A |
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|Buffered switch |Buffer |Yes |Yes |Internal capacitance|
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|Pass-transistor switch|PassTransistor|Yes |Yes |N/A |
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|Wire |Wire |No |Yes |Pi model |
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|Site input pin |Inpin |Yes |No |Input capacitance |
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The elmore delay is the RC tree formed by these 5 components. Out pins and
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buffer switches are the roots of the elmore tree. Buffer switches
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and inpins are leafs of the elmore tree. Wires and pass-transistor switches are
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nodes in the tree. Wires share their capacitance upstream and downstream using
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a pi-model.
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Example timing tree:
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+------+
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|Outpin|
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+--+---+
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v
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+--+--+
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|Wire |
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+--+--+
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+-----------------+
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+--+---+ +-------+------+
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|Buffer| |PassTransistor|
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+--+---+ +------+-------+
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v v
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+--+-+ +--+-+
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|Wire| |Wire|
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+--+-+ +--+-+
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v v
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+--+--+ +--+--+
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|Inpin| |Inpin|
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+-----+ +-----+
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Note on units:
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The timing model operates on the following types of units:
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- Time
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- Resistance
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- Capacitance
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For a consistent unit set, the following equation must be satisfied:
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1 Resistance unit * 1 Capacitance unit = 1 Time unit
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The SI unit set would be:
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- Time = seconds
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- Resistance = Ohms
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- Capacitance = Farads
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However as long as the scale factors are consistent, the model will work
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with other unit combinations. For example:
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- Time = nanoseconds (1e-9 seconds)
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- Resistance = milliOhms (1e-3 Ohms)
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- Capacitance = microFarads (1e-6 Farads)
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(1e-3 * 1e-6) (Ohms * Farads) does equal (1e-9) seconds.
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"""
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import enum
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from collections import namedtuple
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class PvtCorner(enum.Enum):
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""" Process/voltage/temperature corner definitions. """
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# Corner where device operates with fastest intristic delays.
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FAST = "FAST"
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# Corner where device operates with slowest intristic delays.
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SLOW = "SLOW"
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def __lt__(self, other):
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if self.__class__ is other.__class__:
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return self.value < other.value
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return NotImplemented
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class IntristicDelay(namedtuple('IntristicDelay', 'min max')):
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""" An intristic delay instance.
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Represents is the intristic delay through an element (e.g. a site pin or
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interconnect pip).
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The intristic delay of an element is generally modelled at a particular
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"corner" of a design. The "corner" generally speaking is modelled over
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process, voltage and temperature PVT. The IntristicDelay object
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reperesents the minimum or maximum delay through all instances of the
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element at 1 corner.
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Attributes
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----------
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min : float
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Minimum instrinsic delay (nsec)
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max : float
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Maximum instrinsic delay (nsec)
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"""
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class RcElement(namedtuple('RcElement', 'resistance capacitance')):
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""" One part of an RcNode, embedded within an RcTree.
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Attributes
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----------
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resistance : float
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Resistance of element
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capacitance : float
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Capacitance of element
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"""
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pass
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class hashabledict(dict):
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""" Immutable version of dictionary with hash support. """
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def __init__(self, *args, **kwargs):
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super().__init__(*args, **kwargs)
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self.hash = hash(tuple(sorted(self.items())))
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def setdefault(self, *args, **kwargs):
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raise NotImplementedError("hashabledict cannot be mutated.")
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def __setitem__(self, *args, **kwargs):
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raise NotImplementedError("hashabledict cannot be mutated.")
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def update(self, *args, **kwargs):
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raise NotImplementedError("hashabledict cannot be mutated.")
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def __hash__(self):
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return self.hash
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def fast_slow_tuple_to_corners(arr):
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""" Convert delay 4-tuple into two IntristicDelay objects.
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Returns
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-------
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corners : dict of PvtCorner to IntristicDelay
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Dictionary keys of FAST and SLOW, mapping to the instrinsic delay
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for each corner.
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"""
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fast_min, fast_max, slow_min, slow_max = map(float, arr)
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return hashabledict(
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{
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PvtCorner.FAST: IntristicDelay(
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min=fast_min,
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max=fast_max,
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),
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PvtCorner.SLOW: IntristicDelay(
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min=slow_min,
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max=slow_max,
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),
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})
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class TimingNode(object):
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""" Base class for timing node models.
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"""
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def get_intrinsic_delays(self):
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""" Returns Intristic delays (if any) timing node.
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Returns
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-------
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Dictionary of PvtCorner to Intristic. Is None if node has no intristic
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delay.
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"""
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pass
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def get_rc_delay(self):
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""" Return portion of net delay due to elmore (RC) delay at this node.
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Must be called after propigate_delays has been called on the Outpin
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object of this tree.
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"""
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pass
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def get_downstream_cap(self):
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""" Returns downstream capacitance at this node.
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Must be called after propigate_delays has been called on the Outpin
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object of this tree.
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"""
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pass
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def propigate_downstream_capacitance(self, math):
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""" Returns capacitance visible to parent of this node.
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Must call propigate_downstream_capacitance on all children of this node.
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Should save downstream capacitance visible to this node's output
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(if any) to be returned in the get_downstream_cap method.
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"""
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pass
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class DownstreamNode(TimingNode):
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""" All non-root TimingNode's are DownstreamNode's.
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"""
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def propigate_delays(self, elements, math):
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""" Propigates upstream delay elements to children of the tree.
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Must call propigated_delays on all children of this node, and add this
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node to elements.
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Arguments
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---------
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elements : list of TimingNode's
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List of delay nodes between root of this tree and this node.
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math : MathModel
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Math model to use to compute delays
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"""
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pass
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class Outpin(TimingNode):
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""" Represents a site output pin.
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Outpin object is the root of the timing tree. Once tree is built with
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set_sink_wire and Wire.add_child methods, propigate_delays should be
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invoked to estabilish model.
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Arguments
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---------
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resistance
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Drive resistance in elmore delay model
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delays
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Intristic delays on output pin.
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"""
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def __init__(self, resistance, delays):
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self.resistance = resistance
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self.delays = delays
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self.sink_wire = None
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self.downstream_cap = None
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self.rc_delay = None
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def set_sink_wire(self, wire):
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""" Sets sink wire for this output pin.
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An output pin always sinks to exactly 1 wire.
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This method must be called prior to calling propigate_delays method
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on this object.
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Arguments
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---------
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wire : Wire object
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Sink wire for this output pin.
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"""
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self.sink_wire = wire
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def propigate_downstream_capacitance(self, math):
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assert self.sink_wire is not None
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self.downstream_cap = self.sink_wire.propigate_downstream_capacitance(
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math)
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self.rc_delay = math.multiply(self.downstream_cap, self.resistance)
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def propigate_delays(self, math):
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""" Propigate delays throughout tree using specified math model.
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Must be called after elmore tree is estabilished.
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Arguments
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---------
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math : MathModel object
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Math model used when doing timing computations.
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"""
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self.propigate_downstream_capacitance(math)
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self.sink_wire.propigate_delays([self], math)
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self.rc_delay = math.multiply(self.resistance, self.downstream_cap)
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def get_intrinsic_delays(self):
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return self.delays
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def get_rc_delay(self):
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assert self.rc_delay is not None
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return self.rc_delay
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def get_downstream_cap(self):
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assert self.downstream_cap is not None
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return self.downstream_cap
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class Inpin(DownstreamNode):
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""" Represents a site input pin.
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Represents leaf of timing model. Once model is connected and delays
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are propigate (by calling Outpin,propigated_delays), get_delays will
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correctly return the list of delay elements from the root to this leaf.
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Arguments
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---------
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capacitance
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Pin capacitance for input pin.
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delays
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Intristic delays on input pin.
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"""
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def __init__(self, capacitance, delays, name=None):
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self.capacitance = capacitance
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self.delays = delays
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self.propigated_delays = None
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self.name = name
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def get_intrinsic_delays(self):
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return self.delays
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def get_rc_delay(self):
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return None
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def get_downstream_cap(self):
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return None
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def propigate_downstream_capacitance(self, math):
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return self.capacitance
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def propigate_delays(self, elements, math):
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self.propigated_delays = list(elements)
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def get_delays(self):
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""" Return list of delay models that make up the delay for this pin.
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The sum of all delay elements (both intristic and RC) is the net
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delay from the output pin to this input pin.
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"""
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return self.propigated_delays + [self]
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class Wire(DownstreamNode):
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""" Represents a wire in the timing model.
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Wires must be connected to an upstream driver model (Outpin, Buffer,
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PassTransistor objects) with set_sink_wire, and add_child must be called
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attaching output nodes (Buffer, PassTransistor, Inpin objects).
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Arguments
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---------
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rc_elements : List of RcElement
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Resistance and capacitance of this wire.
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math : MathModel
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Math model used to compute lumped resistance and capacitance.
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"""
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def __init__(self, rc_elements, math):
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self.resistance = math.sum(elem.resistance for elem in rc_elements)
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self.capacitance = math.sum(elem.capacitance for elem in rc_elements)
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self.children = []
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self.downstream_cap = None
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self.propigated_delays = None
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self.rc_delay = None
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def add_child(self, child):
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""" Add a child node to this wire.
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Call this method as needed prior to calling propigate_delays on the
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root Outpin object.
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Arguments
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---------
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child : Buffer or PassTransistor or Inpin
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Adds child load to this wire.
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"""
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self.children.append(child)
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def propigate_downstream_capacitance(self, math):
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downstream_cap = math.sum(
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child.propigate_downstream_capacitance(math)
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for child in self.children)
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# Pi-model is definied such that wire resistance only sees half of the
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# wire capacitance.
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self.downstream_cap = math.plus(
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math.divide(self.capacitance, 2), downstream_cap)
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# Upstream seems all of the wires capacitance
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return math.plus(downstream_cap, self.capacitance)
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def propigate_delays(self, elements, math):
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self.propigated_delays = list(elements)
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for child in self.children:
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child.propigate_delays(self.propigated_delays + [self], math)
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self.rc_delay = math.multiply(self.resistance, self.downstream_cap)
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def get_intrinsic_delays(self):
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return None
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def get_rc_delay(self):
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assert self.rc_delay is not None
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return self.rc_delay
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def get_downstream_cap(self):
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assert self.downstream_cap is not None
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return self.downstream_cap
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class Buffer(DownstreamNode):
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""" Represents an isolating switch.
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The internal_capacitance model is such that the upstream node only sees
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the capacitance of this node when the switch is enabled. Therefore, only
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active buffers should be included in the model.
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Arguments
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---------
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internal_capacitance
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Capacitance seen by upstream node when this buffer is enabled.
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drive_resistance
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Driver resistance used for computing elmore delay.
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delays : Dictionary of PvtCorner to IntristicDelay
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Delay through switch
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"""
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def __init__(self, internal_capacitance, drive_resistance, delays):
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self.internal_capacitance = internal_capacitance
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self.drive_resistance = drive_resistance
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self.delays = delays
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self.downstream_cap = None
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self.rc_delay = None
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def set_sink_wire(self, wire):
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""" Sets sink wire for this output pin.
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An output pin always sinks to exactly 1 wire.
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This method must be called prior to calling propigate_delays method
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on the root Outpin object of this tree.
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Arguments
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---------
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wire : Wire object
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Sink wire for this output pin.
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"""
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self.sink_wire = wire
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def propigate_downstream_capacitance(self, math):
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assert self.sink_wire is not None
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self.downstream_cap = self.sink_wire.propigate_downstream_capacitance(
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math)
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return self.internal_capacitance
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def propigate_delays(self, elements, math):
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self.propigated_delays = list(elements)
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assert self.sink_wire is not None
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self.sink_wire.propigate_delays(self.propigated_delays + [self], math)
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self.rc_delay = math.multiply(
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self.downstream_cap, self.drive_resistance)
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def get_intrinsic_delays(self):
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return self.delays
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def get_rc_delay(self):
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assert self.rc_delay is not None
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return self.rc_delay
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def get_downstream_cap(self):
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assert self.downstream_cap is not None
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return self.downstream_cap
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class PassTransistor(DownstreamNode):
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""" Represents a non-isolating switch.
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Arguments
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---------
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drive_resistance
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Driver resistance used for computing elmore delay.
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delays : Dictionary of PvtCorner to IntristicDelay
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Delay through switch.
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"""
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def __init__(self, drive_resistance, delays):
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self.drive_resistance = drive_resistance
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self.delays = delays
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self.sink_wire = None
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self.downstream_cap = None
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self.rc_delay = None
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def set_sink_wire(self, wire):
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""" Sets sink wire for this output pin.
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An output pin always sinks to exactly 1 wire.
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This method must be called prior to calling propigate_delays method
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on the root Outpin object of this tree.
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Arguments
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---------
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wire : Wire object
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Sink wire for this output pin.
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"""
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self.sink_wire = wire
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def propigate_downstream_capacitance(self, math):
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assert self.sink_wire is not None
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self.downstream_cap = self.sink_wire.propigate_downstream_capacitance(
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math)
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return self.downstream_cap
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def propigate_delays(self, elements, math):
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self.propigated_delays = list(elements)
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assert self.sink_wire is not None
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self.sink_wire.propigate_delays(self.propigated_delays + [self], math)
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self.rc_delay = math.multiply(
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self.downstream_cap, self.drive_resistance)
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def get_intrinsic_delays(self):
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return self.delays
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def get_rc_delay(self):
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assert self.rc_delay is not None
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return self.rc_delay
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def get_downstream_cap(self):
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assert self.downstream_cap is not None
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return self.downstream_cap
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