mirror of https://github.com/openXC7/prjxray.git
135 lines
5.2 KiB
ReStructuredText
135 lines
5.2 KiB
ReStructuredText
Glossary
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========================
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.. glossary::
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BEL
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BLE
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Basic element (BEL) or basic logic element (BLE)
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BELs or BLEs are the basic logic elements in an FPGA, including
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carry or fast adders (CFAs), flip flops (FFs), lookup tables (LUTs),
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multiplexers (MUXes), and other element types.
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Note: Programmable interconnects (PIPs) are not counted as BELs.
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BELs come in two forms:
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* Basic BEL - A logic unit which does things.
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* Routing BEL - A unit which is statically configured at routing time.
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Bitstream
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Binary data that is directly loaded into an FPGA to perform configuration.
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Contains configuration :term:`frames <frame>` as well as programming
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sequences and other commands required to load and activate same.
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Clock domain
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Portion of a :term:`horizontal clock row` to one side of the global clock
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spine. Often refers to :term:`tiles <tile>` that are associated with these
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clocks.
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Column
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A term used in :term:`bitstream` configuration to denote
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a collection of :term:`tiles <tile>`, physically organized as
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a vertical line, and configured by the same set of configuration frames.
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Logic columns span 50 tiles vertically and 2 tiles horizontally
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(pairs of logic tiles and interconnect tiles).
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CLB
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Configurable logic block (CLB)
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The configurable logic unit of an FPGA. Also called a **logic cell**.
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A CLB is a combination of basic logic elements (:term:`BELs <BEL>`).
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Database
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A term used in *Project X-Ray* to denote
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text files containing meaningful labels for bit positions within
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:term:`segments <segment>`.
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Frame
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The fundamental unit of :term:`bitstream` configuration data consisting of
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101 :term:`words <word>`.
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Each frame has a 32-bit frame address and 101 payload words, 32 bits each.
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The 50th payload words is an EEC.
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The 7 LSB bits of the frame address are the frame index within the
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configuration :term:`column` (called *minor frame address* in the Xilinx
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documentation). The rest of the frame address identifies the configuration
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column (called *base frame address* in Project X-Ray nomenclature).
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The bits in an individual frame are spread out over the entire column.
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For example, in a logic column with 50 tiles, the first tile is configured
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with the first two words in each frame, the next tile with the next two
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words, and so on.
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Frame base address
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The first configuration frame address for a :term:`column`. A frame base
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address has always the 7 LSB bits cleared.
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Fuzzer
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Scripts and a makefile to generate one or more :term:`specimens <specimen>`
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and then convert the data from those specimens into a :term:`database`.
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Half
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Portion of a device defined by a virtual line dividing the two sets of global
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clock buffers present in a device. The two halves are referred to as
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the top and bottom halves.
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Node
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A routing node on the device. A node is a collection of :term:`wires <wire>`
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spanning one or more "tiles"term" `tiles <tile>`.
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Nodes that are local to a tile map 1:1 to a wire. A node that spans multiple
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tiles maps to multiple wires, one in each tile it spans.
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PIP
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Programmable interconnect point (PIP)
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Connection point between two wires in a tile that may be enabled or
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disabled by the configuration.
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Horizontal clock row
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Portion of a device including 12 horizontal clocks and the 50 interconnect
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and function tiles associated with them. A :term:`half` contains one or
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more horizontal clock rows and each half may have a different number of
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rows.
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ROI
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Region of interest (ROI)
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A term used in *Project X-Ray* to denote a
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rectangular region on the FPGA that is the current focus of our study.
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Right now this is `SLICE_X12Y100:SLICE_X27Y149` on a `xc7a50tfgg484-1`
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chip.
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Segment
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All configuration bits for a horizontal slice of a :term:`column`.
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This corresponds to two ranges: a range of :term:`frames <frame>`
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and a range of :term:`words <word>` within frames. A segment of a logic
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column is 36 frames wide and 2 words high.
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Site
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Portion of a tile where :term:`BELs <BEL>` can be placed. The
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:term:`slices <slice>` in a :term:`CLB` tile are sites.
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Slice
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Portion of a :term:`tile` tile that contains :term:`BELs <BEL>`.
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A `CLBLL_L/CLBLL_R` tile contains two `SLICEL` slices.
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A `CLBLM_L/CLBLM_R` tile contains one `SLICEL` slice and one `SLICEM` slice.
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Specimen
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A :term:`bitstream` of a (usually auto-generated) design with additional
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files containing information about the placed and routed design.
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These additional files are usually generated using Vivado TCL scripts
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querying the Vivado design database.
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Tile
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Fundamental unit of physical structure containing a single type of
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resource or function. A container for :term:`sites <site>` and
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:term:`slices <slice>`. The whole chip is a grid of tiles.
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The most important tile types are left and right interconnect tiles
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(`INT_L` and `INT_R`) and left and right :term:`CLB` logic/memory tiles
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(`CLBLL_L`, `CLBLL_R`, `CLBLM_L`, `CLBLM_R`).
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Wire
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Physical wire within a :term:`tile`.
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Word
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32 bits stored in big-endian order. Fundamental unit of :term:`bitstream`
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format.
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