mirror of https://github.com/openXC7/prjxray.git
94 lines
2.7 KiB
Python
94 lines
2.7 KiB
Python
import os
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import re
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from .roi import Roi
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from .db import Database
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def get_db_root():
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return "%s/%s" % (
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os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))
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def roi_xy():
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x1 = int(os.getenv('XRAY_ROI_GRID_X1'))
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x2 = int(os.getenv('XRAY_ROI_GRID_X2'))
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y1 = int(os.getenv('XRAY_ROI_GRID_Y1'))
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y2 = int(os.getenv('XRAY_ROI_GRID_Y2'))
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return (x1, x2), (y1, y2)
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def slice_xy():
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'''Return (X1, X2), (Y1, Y2) from XRAY_ROI, exclusive end (for xrange)'''
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# SLICE_X12Y100:SLICE_X27Y149
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# Note XRAY_ROI_GRID_* is something else
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m = re.match(
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r'SLICE_X([0-9]*)Y([0-9]*):SLICE_X([0-9]*)Y([0-9]*)',
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os.getenv('XRAY_ROI'))
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ms = [int(m.group(i + 1)) for i in range(4)]
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return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
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def get_roi():
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(x1, x2), (y1, y2) = roi_xy()
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db = Database(get_db_root())
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return Roi(db=db, x1=x1, x2=x2, y1=y1, y2=y2)
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def gen_sites_xy(site_types):
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for _tile_name, site_name, _site_type in get_roi().gen_sites(site_types):
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m = re.match(r'.*_X([0-9]*)Y([0-9]*)', site_name)
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x, y = int(m.group(1)), int(m.group(2))
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yield (site_name, (x, y))
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def site_xy_minmax(site_types):
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'''Return (X1, X2), (Y1, Y2) from XY_ROI, exclusive end (for xrange)'''
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xmin = 9999
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xmax = -1
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ymin = 9999
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ymax = -1
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for _site_name, (x, y) in gen_sites_xy(site_types):
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xmin = min(xmin, x)
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xmax = max(xmax, x)
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ymin = min(ymin, y)
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ymax = max(ymax, y)
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return (xmin, xmax + 1), (ymin, ymax + 1)
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# we know that all bits for CLB MUXes are in frames 30 and 31, so filter all other bits
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def bitfilter_clb_mux(frame_idx, bit_idx):
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return frame_idx in [30, 31]
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def db_root_arg(parser):
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database_dir = os.getenv("XRAY_DATABASE_DIR")
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database = os.getenv("XRAY_DATABASE")
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db_root_kwargs = {}
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if database_dir is None or database is None:
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db_root_kwargs['required'] = True
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else:
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db_root_kwargs['required'] = False
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db_root_kwargs['default'] = os.path.join(database_dir, database)
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parser.add_argument('--db-root', help="Database root.", **db_root_kwargs)
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def parse_db_line(line):
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parts = line.split()
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# Ex: CLBLL_L.SLICEL_X0.AMUX.A5Q
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assert len(parts), "Empty line"
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tag = parts[0]
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assert re.match(r'[A-Z0-9_.]+',
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tag), "Invalid tag name: %s, line: %s" % (tag, line)
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orig_bits = line.replace(tag + " ", "")
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# <0 candidates> etc
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if "<" in orig_bits:
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return tag, set(), orig_bits
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# Ex: !30_06 !30_08 !30_11 30_07
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bits = frozenset(parts[1:])
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for bit in bits:
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assert re.match(
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r'[!]*[0-9][0-9]_[0-9][0-9]', bit), "Invalid bit: %s" % bit
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return tag, bits, None
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