mirror of https://github.com/openXC7/prjxray.git
11906 lines
256 KiB
JSON
11906 lines
256 KiB
JSON
[
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
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|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y2\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y2\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y2",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y1\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y1\"",
|
|
"TILE_NAME": "LIOB18_X81Y2"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y3\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y3\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y4",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y4\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y4\"",
|
|
"TILE_NAME": "LIOB18_X81Y4"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 8,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y6\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y6\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
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|
"SRVAL_Q4": 1,
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|
"TILE_NAME": "LIOB18_X81Y6",
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|
"USE_IDELAY": 0
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|
},
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|
{
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|
"IDELAY_LOC": "\"IDELAY_X0Y5\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y5\"",
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|
"TILE_NAME": "LIOB18_X81Y6"
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|
}
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|
],
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|
[
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{
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"BEL_TYPE": "\"IDDR\"",
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|
"CE1USED": 0,
|
|
"CHAINED": 0,
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|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y8\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y8\"",
|
|
"SRTYPE": "\"ASYNC\"",
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|
"SR_MODE": "\"NONE\"",
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|
"TILE_NAME": "LIOB18_X81Y8",
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"USE_IDELAY": 1
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|
},
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{
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"IDELAY_LOC": "\"IDELAY_X0Y7\"",
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"IS_USED": 0,
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|
"SITE_LOC": "\"ILOGIC_X0Y7\"",
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|
"TILE_NAME": "LIOB18_X81Y8"
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|
}
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|
],
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|
[
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{
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"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y9\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y9\"",
|
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"SRTYPE": "\"SYNC\"",
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"SR_MODE": "\"RST\"",
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"TILE_NAME": "LIOB18_X81Y10",
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"USE_IDELAY": 1
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|
},
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|
{
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"IDELAY_LOC": "\"IDELAY_X0Y10\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y10\"",
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|
"TILE_NAME": "LIOB18_X81Y10"
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}
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],
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[
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{
|
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"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y12\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y12\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
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|
"TILE_NAME": "LIOB18_X81Y12",
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"USE_IDELAY": 0
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|
},
|
|
{
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"IDELAY_LOC": "\"IDELAY_X0Y11\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y11\"",
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"TILE_NAME": "LIOB18_X81Y12"
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}
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],
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[
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{
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"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y13\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y13\"",
|
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"SRTYPE": "\"SYNC\"",
|
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"SR_MODE": "\"SET\"",
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|
"TILE_NAME": "LIOB18_X81Y14",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
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"IDELAY_LOC": "\"IDELAY_X0Y14\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y14\"",
|
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"TILE_NAME": "LIOB18_X81Y14"
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}
|
|
],
|
|
[
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|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y15\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y15\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y16",
|
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"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y16\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y16\"",
|
|
"TILE_NAME": "LIOB18_X81Y16"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y18\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y18\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y18",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y17\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y17\"",
|
|
"TILE_NAME": "LIOB18_X81Y18"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y20\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y20\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y20",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y19\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y19\"",
|
|
"TILE_NAME": "LIOB18_X81Y20"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y21\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y21\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y22",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y22\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y22\"",
|
|
"TILE_NAME": "LIOB18_X81Y22"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y23\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y23\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y24",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y24\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y24\"",
|
|
"TILE_NAME": "LIOB18_X81Y24"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 8,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y26\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y26\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y27",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y25\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y25\"",
|
|
"TILE_NAME": "LIOB18_X81Y27"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y28\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y28\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y29",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y27\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y27\"",
|
|
"TILE_NAME": "LIOB18_X81Y29"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y29\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y29\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y31",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y30\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y30\"",
|
|
"TILE_NAME": "LIOB18_X81Y31"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y32\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y32\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y33",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y31\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y31\"",
|
|
"TILE_NAME": "LIOB18_X81Y33"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y34\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y34\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y35",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y33\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y33\"",
|
|
"TILE_NAME": "LIOB18_X81Y35"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y35\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y35\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y37",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y36\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y36\"",
|
|
"TILE_NAME": "LIOB18_X81Y37"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 8,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y37\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y37\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y39",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y38\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y38\"",
|
|
"TILE_NAME": "LIOB18_X81Y39"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y39\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y39\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y41",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y40\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y40\"",
|
|
"TILE_NAME": "LIOB18_X81Y41"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y42\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y42\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y43",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y41\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y41\"",
|
|
"TILE_NAME": "LIOB18_X81Y43"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y44\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y44\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y45",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y43\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y43\"",
|
|
"TILE_NAME": "LIOB18_X81Y45"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y45\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y45\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y47",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y46\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y46\"",
|
|
"TILE_NAME": "LIOB18_X81Y47"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y48\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y48\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y49",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y47\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y47\"",
|
|
"TILE_NAME": "LIOB18_X81Y49"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y52\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y52\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y54",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y51\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y51\"",
|
|
"TILE_NAME": "LIOB18_X81Y54"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y53\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y53\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y56",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y54\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y54\"",
|
|
"TILE_NAME": "LIOB18_X81Y56"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y56\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y56\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y58",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y55\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y55\"",
|
|
"TILE_NAME": "LIOB18_X81Y58"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y58\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y58\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y60",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y57\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y57\"",
|
|
"TILE_NAME": "LIOB18_X81Y60"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y60\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y60\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y62",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y59\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y59\"",
|
|
"TILE_NAME": "LIOB18_X81Y62"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y62\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y62\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y64",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y61\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y61\"",
|
|
"TILE_NAME": "LIOB18_X81Y64"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y63\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y63\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y66",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y64\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y64\"",
|
|
"TILE_NAME": "LIOB18_X81Y66"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y66\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y66\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y68",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y65\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y65\"",
|
|
"TILE_NAME": "LIOB18_X81Y68"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y67\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y67\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y70",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y68\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y68\"",
|
|
"TILE_NAME": "LIOB18_X81Y70"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y69\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y69\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y72",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y70\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y70\"",
|
|
"TILE_NAME": "LIOB18_X81Y72"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y71\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y71\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y74",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y72\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y72\"",
|
|
"TILE_NAME": "LIOB18_X81Y74"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y74\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y74\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y76",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y73\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y73\"",
|
|
"TILE_NAME": "LIOB18_X81Y76"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 8,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y76\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y76\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y79",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y75\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y75\"",
|
|
"TILE_NAME": "LIOB18_X81Y79"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y77\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y77\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y81",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y78\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y78\"",
|
|
"TILE_NAME": "LIOB18_X81Y81"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 10,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y79\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y79\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y83",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y80\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y80\"",
|
|
"TILE_NAME": "LIOB18_X81Y83"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y82\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y82\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y85",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y81\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y81\"",
|
|
"TILE_NAME": "LIOB18_X81Y85"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y84\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y84\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y87",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y83\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y83\"",
|
|
"TILE_NAME": "LIOB18_X81Y87"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y86\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y86\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y89",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y85\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y85\"",
|
|
"TILE_NAME": "LIOB18_X81Y89"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y87\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y87\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y91",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y88\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y88\"",
|
|
"TILE_NAME": "LIOB18_X81Y91"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y90\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y90\"",
|
|
"TILE_NAME": "LIOB18_X81Y93"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y89\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y89\"",
|
|
"TILE_NAME": "LIOB18_X81Y93"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y92\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y92\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y95",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y91\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y91\"",
|
|
"TILE_NAME": "LIOB18_X81Y95"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y94\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y94\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y97",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y93\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y93\"",
|
|
"TILE_NAME": "LIOB18_X81Y97"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y96\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y96\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y99",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y95\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y95\"",
|
|
"TILE_NAME": "LIOB18_X81Y99"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y98\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y98\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y101",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y97\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y97\"",
|
|
"TILE_NAME": "LIOB18_X81Y101"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y102\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y102\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y106",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y101\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y101\"",
|
|
"TILE_NAME": "LIOB18_X81Y106"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y104\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y104\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y108",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y103\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y103\"",
|
|
"TILE_NAME": "LIOB18_X81Y108"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y106\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y106\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y110",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y105\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y105\"",
|
|
"TILE_NAME": "LIOB18_X81Y110"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y108\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y108\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y112",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y107\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y107\"",
|
|
"TILE_NAME": "LIOB18_X81Y112"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y110\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y110\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y114",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y109\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y109\"",
|
|
"TILE_NAME": "LIOB18_X81Y114"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y111\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y111\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y116",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y112\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y112\"",
|
|
"TILE_NAME": "LIOB18_X81Y116"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y114\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y114\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y118",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y113\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y113\"",
|
|
"TILE_NAME": "LIOB18_X81Y118"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y116\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y116\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y120",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y115\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y115\"",
|
|
"TILE_NAME": "LIOB18_X81Y120"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y118\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y118\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y122",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y117\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y117\"",
|
|
"TILE_NAME": "LIOB18_X81Y122"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y119\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y119\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y124",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y120\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y120\"",
|
|
"TILE_NAME": "LIOB18_X81Y124"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 8,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y122\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y122\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y126",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y121\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y121\"",
|
|
"TILE_NAME": "LIOB18_X81Y126"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y124\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y124\"",
|
|
"TILE_NAME": "LIOB18_X81Y128"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y123\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y123\"",
|
|
"TILE_NAME": "LIOB18_X81Y128"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y126\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y126\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y131",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y125\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y125\"",
|
|
"TILE_NAME": "LIOB18_X81Y131"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y127\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y127\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y133",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y128\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y128\"",
|
|
"TILE_NAME": "LIOB18_X81Y133"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y130\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y130\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y135",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y129\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y129\"",
|
|
"TILE_NAME": "LIOB18_X81Y135"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y132\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y132\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y137",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y131\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y131\"",
|
|
"TILE_NAME": "LIOB18_X81Y137"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y134\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y134\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y139",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y133\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y133\"",
|
|
"TILE_NAME": "LIOB18_X81Y139"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y136\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y136\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y141",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y135\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y135\"",
|
|
"TILE_NAME": "LIOB18_X81Y141"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y137\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y137\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y143",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y138\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y138\"",
|
|
"TILE_NAME": "LIOB18_X81Y143"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y140\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y140\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y145",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y139\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y139\"",
|
|
"TILE_NAME": "LIOB18_X81Y145"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y142\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y142\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y147",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y141\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y141\"",
|
|
"TILE_NAME": "LIOB18_X81Y147"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y143\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y143\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y149",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y144\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y144\"",
|
|
"TILE_NAME": "LIOB18_X81Y149"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y146\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y146\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y151",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y145\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y145\"",
|
|
"TILE_NAME": "LIOB18_X81Y151"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y147\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y147\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y153",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y148\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y148\"",
|
|
"TILE_NAME": "LIOB18_X81Y153"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y152\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y152\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y158",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y151\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y151\"",
|
|
"TILE_NAME": "LIOB18_X81Y158"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y154\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y154\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y160",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y153\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y153\"",
|
|
"TILE_NAME": "LIOB18_X81Y160"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y155\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y155\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y162",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y156\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y156\"",
|
|
"TILE_NAME": "LIOB18_X81Y162"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y158\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y158\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y164",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y157\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y157\"",
|
|
"TILE_NAME": "LIOB18_X81Y164"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y160\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y160\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y166",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y159\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y159\"",
|
|
"TILE_NAME": "LIOB18_X81Y166"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y162\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y162\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y168",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y161\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y161\"",
|
|
"TILE_NAME": "LIOB18_X81Y168"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y163\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y163\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y170",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y164\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y164\"",
|
|
"TILE_NAME": "LIOB18_X81Y170"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y166\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y166\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y172",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y165\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y165\"",
|
|
"TILE_NAME": "LIOB18_X81Y172"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y168\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y168\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y174",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y167\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y167\"",
|
|
"TILE_NAME": "LIOB18_X81Y174"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y170\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y170\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y176",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y169\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y169\"",
|
|
"TILE_NAME": "LIOB18_X81Y176"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y171\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y171\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y178",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y172\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y172\"",
|
|
"TILE_NAME": "LIOB18_X81Y178"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y173\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y173\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y180",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y174\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y174\"",
|
|
"TILE_NAME": "LIOB18_X81Y180"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y175\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y175\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y183",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y176\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y176\"",
|
|
"TILE_NAME": "LIOB18_X81Y183"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y178\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y178\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y185",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y177\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y177\"",
|
|
"TILE_NAME": "LIOB18_X81Y185"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y180\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y180\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y187",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y179\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y179\"",
|
|
"TILE_NAME": "LIOB18_X81Y187"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y181\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y181\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y189",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y182\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y182\"",
|
|
"TILE_NAME": "LIOB18_X81Y189"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y184\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y184\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y191",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y183\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y183\"",
|
|
"TILE_NAME": "LIOB18_X81Y191"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y185\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y185\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y193",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y186\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y186\"",
|
|
"TILE_NAME": "LIOB18_X81Y193"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 6,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y187\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y187\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y195",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y188\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y188\"",
|
|
"TILE_NAME": "LIOB18_X81Y195"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y189\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y189\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y197",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y190\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y190\"",
|
|
"TILE_NAME": "LIOB18_X81Y197"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y192\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y192\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y199",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y191\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y191\"",
|
|
"TILE_NAME": "LIOB18_X81Y199"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y193\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y193\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y201",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y194\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y194\"",
|
|
"TILE_NAME": "LIOB18_X81Y201"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y196\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y196\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y203",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y195\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y195\"",
|
|
"TILE_NAME": "LIOB18_X81Y203"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y197\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y197\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y205",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y198\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y198\"",
|
|
"TILE_NAME": "LIOB18_X81Y205"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y201\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y201\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y210",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y202\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y202\"",
|
|
"TILE_NAME": "LIOB18_X81Y210"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y204\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y204\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y212",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y203\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y203\"",
|
|
"TILE_NAME": "LIOB18_X81Y212"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y206\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y206\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y214",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y205\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y205\"",
|
|
"TILE_NAME": "LIOB18_X81Y214"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y208\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y208\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y216",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y207\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y207\"",
|
|
"TILE_NAME": "LIOB18_X81Y216"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y210\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y210\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y218",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y209\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y209\"",
|
|
"TILE_NAME": "LIOB18_X81Y218"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y212\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y212\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y220",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y211\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y211\"",
|
|
"TILE_NAME": "LIOB18_X81Y220"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y214\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y214\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y222",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y213\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y213\"",
|
|
"TILE_NAME": "LIOB18_X81Y222"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y215\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y215\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y224",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y216\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y216\"",
|
|
"TILE_NAME": "LIOB18_X81Y224"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y218\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y218\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y226",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y217\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y217\"",
|
|
"TILE_NAME": "LIOB18_X81Y226"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y220\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y220\"",
|
|
"TILE_NAME": "LIOB18_X81Y228"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y219\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y219\"",
|
|
"TILE_NAME": "LIOB18_X81Y228"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y222\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y222\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y230",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y221\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y221\"",
|
|
"TILE_NAME": "LIOB18_X81Y230"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y224\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y224\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y232",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y223\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y223\"",
|
|
"TILE_NAME": "LIOB18_X81Y232"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y226\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y226\"",
|
|
"TILE_NAME": "LIOB18_X81Y235"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y225\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y225\"",
|
|
"TILE_NAME": "LIOB18_X81Y235"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y228\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y228\"",
|
|
"TILE_NAME": "LIOB18_X81Y237"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y227\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y227\"",
|
|
"TILE_NAME": "LIOB18_X81Y237"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y230\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y230\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y239",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y229\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y229\"",
|
|
"TILE_NAME": "LIOB18_X81Y239"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y231\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y231\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y241",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y232\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y232\"",
|
|
"TILE_NAME": "LIOB18_X81Y241"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y233\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y233\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y243",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y234\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y234\"",
|
|
"TILE_NAME": "LIOB18_X81Y243"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y235\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y235\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y245",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y236\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y236\"",
|
|
"TILE_NAME": "LIOB18_X81Y245"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 5,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y237\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y237\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y247",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y238\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y238\"",
|
|
"TILE_NAME": "LIOB18_X81Y247"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y240\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y240\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y249",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y239\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y239\"",
|
|
"TILE_NAME": "LIOB18_X81Y249"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y242\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y242\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y251",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y241\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y241\"",
|
|
"TILE_NAME": "LIOB18_X81Y251"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y244\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y244\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y253",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y243\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y243\"",
|
|
"TILE_NAME": "LIOB18_X81Y253"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y245\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y245\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y255",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y246\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y246\"",
|
|
"TILE_NAME": "LIOB18_X81Y255"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y247\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y247\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y257",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y248\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y248\"",
|
|
"TILE_NAME": "LIOB18_X81Y257"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y252\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y252\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y262",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y251\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y251\"",
|
|
"TILE_NAME": "LIOB18_X81Y262"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y254\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y254\"",
|
|
"TILE_NAME": "LIOB18_X81Y264"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y253\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y253\"",
|
|
"TILE_NAME": "LIOB18_X81Y264"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y255\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y255\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y266",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y256\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y256\"",
|
|
"TILE_NAME": "LIOB18_X81Y266"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y257\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y257\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y268",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y258\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y258\"",
|
|
"TILE_NAME": "LIOB18_X81Y268"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y259\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y259\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y270",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y260\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y260\"",
|
|
"TILE_NAME": "LIOB18_X81Y270"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y262\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y262\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y272",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y261\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y261\"",
|
|
"TILE_NAME": "LIOB18_X81Y272"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y264\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y264\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y274",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y263\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y263\"",
|
|
"TILE_NAME": "LIOB18_X81Y274"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y265\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y265\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y276",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y266\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y266\"",
|
|
"TILE_NAME": "LIOB18_X81Y276"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y267\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y267\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y278",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y268\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y268\"",
|
|
"TILE_NAME": "LIOB18_X81Y278"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y270\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y270\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y280",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y269\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y269\"",
|
|
"TILE_NAME": "LIOB18_X81Y280"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y272\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y272\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y282",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y271\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y271\"",
|
|
"TILE_NAME": "LIOB18_X81Y282"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y273\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y273\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y284",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y274\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y274\"",
|
|
"TILE_NAME": "LIOB18_X81Y284"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y276\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y276\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y287",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y275\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y275\"",
|
|
"TILE_NAME": "LIOB18_X81Y287"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y277\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y277\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y289",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y278\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y278\"",
|
|
"TILE_NAME": "LIOB18_X81Y289"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y279\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y279\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y291",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y280\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y280\"",
|
|
"TILE_NAME": "LIOB18_X81Y291"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y281\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y281\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y293",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y282\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y282\"",
|
|
"TILE_NAME": "LIOB18_X81Y293"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y283\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y283\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y295",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y284\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y284\"",
|
|
"TILE_NAME": "LIOB18_X81Y295"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y286\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y286\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y297",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y285\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y285\"",
|
|
"TILE_NAME": "LIOB18_X81Y297"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y287\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y287\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y299",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y288\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y288\"",
|
|
"TILE_NAME": "LIOB18_X81Y299"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y289\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y289\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y301",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y290\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y290\"",
|
|
"TILE_NAME": "LIOB18_X81Y301"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y291\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y291\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y303",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y292\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y292\"",
|
|
"TILE_NAME": "LIOB18_X81Y303"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y294\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y294\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y305",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y293\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y293\"",
|
|
"TILE_NAME": "LIOB18_X81Y305"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y295\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y295\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y307",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y296\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y296\"",
|
|
"TILE_NAME": "LIOB18_X81Y307"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y298\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y298\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y309",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y297\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y297\"",
|
|
"TILE_NAME": "LIOB18_X81Y309"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y302\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y302\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y314",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y301\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y301\"",
|
|
"TILE_NAME": "LIOB18_X81Y314"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y303\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y303\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y316",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y304\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y304\"",
|
|
"TILE_NAME": "LIOB18_X81Y316"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y306\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y306\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y318",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y305\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y305\"",
|
|
"TILE_NAME": "LIOB18_X81Y318"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y308\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y308\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y320",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y307\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y307\"",
|
|
"TILE_NAME": "LIOB18_X81Y320"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y310\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y310\"",
|
|
"TILE_NAME": "LIOB18_X81Y322"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y309\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y309\"",
|
|
"TILE_NAME": "LIOB18_X81Y322"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 6,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y312\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y312\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y324",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y311\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y311\"",
|
|
"TILE_NAME": "LIOB18_X81Y324"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y313\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y313\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y326",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y314\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y314\"",
|
|
"TILE_NAME": "LIOB18_X81Y326"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y315\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y315\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y328",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y316\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y316\"",
|
|
"TILE_NAME": "LIOB18_X81Y328"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y318\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y318\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y330",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y317\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y317\"",
|
|
"TILE_NAME": "LIOB18_X81Y330"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 2,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y319\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y319\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y332",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y320\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y320\"",
|
|
"TILE_NAME": "LIOB18_X81Y332"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y321\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y321\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "LIOB18_X81Y334",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y322\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y322\"",
|
|
"TILE_NAME": "LIOB18_X81Y334"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y323\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y323\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y336",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y324\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y324\"",
|
|
"TILE_NAME": "LIOB18_X81Y336"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y325\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y325\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y339",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y326\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y326\"",
|
|
"TILE_NAME": "LIOB18_X81Y339"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 14,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y327\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y327\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y341",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y328\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y328\"",
|
|
"TILE_NAME": "LIOB18_X81Y341"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y330\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y330\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y343",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y329\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y329\"",
|
|
"TILE_NAME": "LIOB18_X81Y343"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y332\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y332\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "LIOB18_X81Y345",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y331\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y331\"",
|
|
"TILE_NAME": "LIOB18_X81Y345"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y334\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y334\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y347",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y333\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y333\"",
|
|
"TILE_NAME": "LIOB18_X81Y347"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y336\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y336\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y349",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y335\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y335\"",
|
|
"TILE_NAME": "LIOB18_X81Y349"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 14,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y337\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y337\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y351",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y338\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y338\"",
|
|
"TILE_NAME": "LIOB18_X81Y351"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y339\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X0Y339\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "LIOB18_X81Y353",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y340\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y340\"",
|
|
"TILE_NAME": "LIOB18_X81Y353"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 6,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y341\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y341\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y355",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y342\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y342\"",
|
|
"TILE_NAME": "LIOB18_X81Y355"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y344\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y344\"",
|
|
"TILE_NAME": "LIOB18_X81Y357"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y343\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y343\"",
|
|
"TILE_NAME": "LIOB18_X81Y357"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y345\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y345\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "LIOB18_X81Y359",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y346\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y346\"",
|
|
"TILE_NAME": "LIOB18_X81Y359"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X0Y348\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X0Y348\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "LIOB18_X81Y361",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X0Y347\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X0Y347\"",
|
|
"TILE_NAME": "LIOB18_X81Y361"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y2\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y2\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y2",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y1\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y1\"",
|
|
"TILE_NAME": "RIOB18_X312Y2"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y3\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y3\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y4",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y4\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y4\"",
|
|
"TILE_NAME": "RIOB18_X312Y4"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y6\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y6\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y6",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y5\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y5\"",
|
|
"TILE_NAME": "RIOB18_X312Y6"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y7\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y7\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y8",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y8\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y8\"",
|
|
"TILE_NAME": "RIOB18_X312Y8"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y10\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y10\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y10",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y9\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y9\"",
|
|
"TILE_NAME": "RIOB18_X312Y10"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y12\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y12\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y12",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y11\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y11\"",
|
|
"TILE_NAME": "RIOB18_X312Y12"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y14\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y14\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y14",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y13\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y13\"",
|
|
"TILE_NAME": "RIOB18_X312Y14"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y15\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y15\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y16",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y16\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y16\"",
|
|
"TILE_NAME": "RIOB18_X312Y16"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y17\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y17\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y18",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y18\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y18\"",
|
|
"TILE_NAME": "RIOB18_X312Y18"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y20\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y20\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y20",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y19\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y19\"",
|
|
"TILE_NAME": "RIOB18_X312Y20"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y21\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y21\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y22",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y22\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y22\"",
|
|
"TILE_NAME": "RIOB18_X312Y22"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y23\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y23\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y24",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y24\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y24\"",
|
|
"TILE_NAME": "RIOB18_X312Y24"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y26\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y26\"",
|
|
"TILE_NAME": "RIOB18_X312Y27"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y25\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y25\"",
|
|
"TILE_NAME": "RIOB18_X312Y27"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y28\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y28\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y29",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y27\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y27\"",
|
|
"TILE_NAME": "RIOB18_X312Y29"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 5,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y29\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y29\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y31",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y30\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y30\"",
|
|
"TILE_NAME": "RIOB18_X312Y31"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y32\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y32\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y33",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y31\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y31\"",
|
|
"TILE_NAME": "RIOB18_X312Y33"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y34\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y34\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y35",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y33\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y33\"",
|
|
"TILE_NAME": "RIOB18_X312Y35"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y35\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y35\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y37",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y36\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y36\"",
|
|
"TILE_NAME": "RIOB18_X312Y37"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y37\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y37\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y39",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y38\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y38\"",
|
|
"TILE_NAME": "RIOB18_X312Y39"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y39\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y39\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y41",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y40\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y40\"",
|
|
"TILE_NAME": "RIOB18_X312Y41"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y41\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y41\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y43",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y42\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y42\"",
|
|
"TILE_NAME": "RIOB18_X312Y43"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y44\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y44\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y45",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y43\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y43\"",
|
|
"TILE_NAME": "RIOB18_X312Y45"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 10,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y45\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y45\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y47",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y46\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y46\"",
|
|
"TILE_NAME": "RIOB18_X312Y47"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y48\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y48\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y49",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y47\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y47\"",
|
|
"TILE_NAME": "RIOB18_X312Y49"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y51\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y51\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y54",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y52\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y52\"",
|
|
"TILE_NAME": "RIOB18_X312Y54"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 7,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y53\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y53\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y56",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y54\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y54\"",
|
|
"TILE_NAME": "RIOB18_X312Y56"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y55\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y55\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y58",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y56\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y56\"",
|
|
"TILE_NAME": "RIOB18_X312Y58"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y57\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y57\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y60",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y58\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y58\"",
|
|
"TILE_NAME": "RIOB18_X312Y60"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y60\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y60\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y62",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y59\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y59\"",
|
|
"TILE_NAME": "RIOB18_X312Y62"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 8,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y61\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y61\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y64",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y62\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y62\"",
|
|
"TILE_NAME": "RIOB18_X312Y64"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y63\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y63\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y66",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y64\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y64\"",
|
|
"TILE_NAME": "RIOB18_X312Y66"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y65\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y65\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y68",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y66\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y66\"",
|
|
"TILE_NAME": "RIOB18_X312Y68"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y67\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y67\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y70",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y68\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y68\"",
|
|
"TILE_NAME": "RIOB18_X312Y70"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y70\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y70\"",
|
|
"TILE_NAME": "RIOB18_X312Y72"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y69\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y69\"",
|
|
"TILE_NAME": "RIOB18_X312Y72"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y72\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y72\"",
|
|
"TILE_NAME": "RIOB18_X312Y74"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y71\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y71\"",
|
|
"TILE_NAME": "RIOB18_X312Y74"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y74\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y74\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y76",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y73\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y73\"",
|
|
"TILE_NAME": "RIOB18_X312Y76"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y76\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y76\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y79",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y75\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y75\"",
|
|
"TILE_NAME": "RIOB18_X312Y79"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y78\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y78\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y81",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y77\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y77\"",
|
|
"TILE_NAME": "RIOB18_X312Y81"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y79\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y79\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y83",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y80\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y80\"",
|
|
"TILE_NAME": "RIOB18_X312Y83"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y81\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y81\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y85",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y82\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y82\"",
|
|
"TILE_NAME": "RIOB18_X312Y85"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y84\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y84\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y87",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y83\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y83\"",
|
|
"TILE_NAME": "RIOB18_X312Y87"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y85\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y85\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y89",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y86\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y86\"",
|
|
"TILE_NAME": "RIOB18_X312Y89"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y87\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y87\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y91",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y88\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y88\"",
|
|
"TILE_NAME": "RIOB18_X312Y91"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y90\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y90\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y93",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y89\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y89\"",
|
|
"TILE_NAME": "RIOB18_X312Y93"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y92\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y92\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y95",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y91\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y91\"",
|
|
"TILE_NAME": "RIOB18_X312Y95"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y93\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y93\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y97",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y94\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y94\"",
|
|
"TILE_NAME": "RIOB18_X312Y97"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y96\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y96\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y99",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y95\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y95\"",
|
|
"TILE_NAME": "RIOB18_X312Y99"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y98\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y98\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y101",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y97\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y97\"",
|
|
"TILE_NAME": "RIOB18_X312Y101"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y102\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y102\"",
|
|
"TILE_NAME": "RIOB18_X312Y106"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y101\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y101\"",
|
|
"TILE_NAME": "RIOB18_X312Y106"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y103\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y103\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y108",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y104\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y104\"",
|
|
"TILE_NAME": "RIOB18_X312Y108"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y106\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y106\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y110",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y105\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y105\"",
|
|
"TILE_NAME": "RIOB18_X312Y110"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y107\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y107\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y112",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y108\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y108\"",
|
|
"TILE_NAME": "RIOB18_X312Y112"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 5,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y109\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y109\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y114",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y110\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y110\"",
|
|
"TILE_NAME": "RIOB18_X312Y114"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y111\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y111\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y116",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y112\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y112\"",
|
|
"TILE_NAME": "RIOB18_X312Y116"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y114\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y114\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y118",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y113\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y113\"",
|
|
"TILE_NAME": "RIOB18_X312Y118"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y115\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y115\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y120",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y116\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y116\"",
|
|
"TILE_NAME": "RIOB18_X312Y120"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y117\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y117\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y122",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y118\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y118\"",
|
|
"TILE_NAME": "RIOB18_X312Y122"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y119\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y119\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y124",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y120\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y120\"",
|
|
"TILE_NAME": "RIOB18_X312Y124"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 10,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y121\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y121\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y126",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y122\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y122\"",
|
|
"TILE_NAME": "RIOB18_X312Y126"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y123\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y123\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y128",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y124\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y124\"",
|
|
"TILE_NAME": "RIOB18_X312Y128"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y125\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y125\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y131",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y126\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y126\"",
|
|
"TILE_NAME": "RIOB18_X312Y131"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y128\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y128\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y133",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y127\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y127\"",
|
|
"TILE_NAME": "RIOB18_X312Y133"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y129\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y129\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y135",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y130\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y130\"",
|
|
"TILE_NAME": "RIOB18_X312Y135"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y132\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y132\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y137",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y131\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y131\"",
|
|
"TILE_NAME": "RIOB18_X312Y137"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y133\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y133\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y139",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y134\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y134\"",
|
|
"TILE_NAME": "RIOB18_X312Y139"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y136\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y136\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y141",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y135\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y135\"",
|
|
"TILE_NAME": "RIOB18_X312Y141"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y138\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y138\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y143",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y137\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y137\"",
|
|
"TILE_NAME": "RIOB18_X312Y143"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y139\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y139\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y145",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y140\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y140\"",
|
|
"TILE_NAME": "RIOB18_X312Y145"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y141\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y141\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y147",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y142\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y142\"",
|
|
"TILE_NAME": "RIOB18_X312Y147"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y144\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y144\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y149",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y143\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y143\"",
|
|
"TILE_NAME": "RIOB18_X312Y149"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y146\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y146\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y151",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y145\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y145\"",
|
|
"TILE_NAME": "RIOB18_X312Y151"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y148\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y148\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y153",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y147\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y147\"",
|
|
"TILE_NAME": "RIOB18_X312Y153"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y152\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y152\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y158",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y151\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y151\"",
|
|
"TILE_NAME": "RIOB18_X312Y158"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y154\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y154\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y160",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y153\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y153\"",
|
|
"TILE_NAME": "RIOB18_X312Y160"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y156\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y156\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y162",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y155\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y155\"",
|
|
"TILE_NAME": "RIOB18_X312Y162"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y158\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y158\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y164",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y157\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y157\"",
|
|
"TILE_NAME": "RIOB18_X312Y164"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y160\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y160\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y166",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y159\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y159\"",
|
|
"TILE_NAME": "RIOB18_X312Y166"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y161\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y161\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y168",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y162\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y162\"",
|
|
"TILE_NAME": "RIOB18_X312Y168"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y163\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y163\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y170",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y164\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y164\"",
|
|
"TILE_NAME": "RIOB18_X312Y170"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y166\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y166\"",
|
|
"TILE_NAME": "RIOB18_X312Y172"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y165\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y165\"",
|
|
"TILE_NAME": "RIOB18_X312Y172"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y168\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y168\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y174",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y167\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y167\"",
|
|
"TILE_NAME": "RIOB18_X312Y174"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y170\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y170\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y176",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y169\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y169\"",
|
|
"TILE_NAME": "RIOB18_X312Y176"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y172\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y172\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y178",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y171\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y171\"",
|
|
"TILE_NAME": "RIOB18_X312Y178"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y173\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y173\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y180",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y174\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y174\"",
|
|
"TILE_NAME": "RIOB18_X312Y180"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y176\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y176\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y183",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y175\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y175\"",
|
|
"TILE_NAME": "RIOB18_X312Y183"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y177\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y177\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y185",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y178\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y178\"",
|
|
"TILE_NAME": "RIOB18_X312Y185"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y180\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y180\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y187",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y179\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y179\"",
|
|
"TILE_NAME": "RIOB18_X312Y187"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 14,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y182\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y182\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y189",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y181\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y181\"",
|
|
"TILE_NAME": "RIOB18_X312Y189"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y184\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y184\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y191",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y183\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y183\"",
|
|
"TILE_NAME": "RIOB18_X312Y191"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y185\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y185\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y193",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y186\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y186\"",
|
|
"TILE_NAME": "RIOB18_X312Y193"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y188\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y188\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y195",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y187\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y187\"",
|
|
"TILE_NAME": "RIOB18_X312Y195"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y189\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y189\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y197",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y190\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y190\"",
|
|
"TILE_NAME": "RIOB18_X312Y197"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y191\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y191\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y199",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y192\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y192\"",
|
|
"TILE_NAME": "RIOB18_X312Y199"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y193\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y193\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y201",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y194\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y194\"",
|
|
"TILE_NAME": "RIOB18_X312Y201"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y196\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y196\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y203",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y195\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y195\"",
|
|
"TILE_NAME": "RIOB18_X312Y203"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y198\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y198\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y205",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y197\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y197\"",
|
|
"TILE_NAME": "RIOB18_X312Y205"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y202\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y202\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y210",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y201\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y201\"",
|
|
"TILE_NAME": "RIOB18_X312Y210"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y203\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y203\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y212",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y204\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y204\"",
|
|
"TILE_NAME": "RIOB18_X312Y212"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y206\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y206\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y214",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y205\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y205\"",
|
|
"TILE_NAME": "RIOB18_X312Y214"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 8,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y207\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y207\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y216",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y208\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y208\"",
|
|
"TILE_NAME": "RIOB18_X312Y216"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y210\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y210\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y218",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y209\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y209\"",
|
|
"TILE_NAME": "RIOB18_X312Y218"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y211\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y211\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y220",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y212\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y212\"",
|
|
"TILE_NAME": "RIOB18_X312Y220"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y213\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y213\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y222",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y214\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y214\"",
|
|
"TILE_NAME": "RIOB18_X312Y222"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y216\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y216\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y224",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y215\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y215\"",
|
|
"TILE_NAME": "RIOB18_X312Y224"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y218\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y218\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y226",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y217\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y217\"",
|
|
"TILE_NAME": "RIOB18_X312Y226"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y220\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y220\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y228",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y219\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y219\"",
|
|
"TILE_NAME": "RIOB18_X312Y228"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y221\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y221\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y230",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y222\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y222\"",
|
|
"TILE_NAME": "RIOB18_X312Y230"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y224\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y224\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y232",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y223\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y223\"",
|
|
"TILE_NAME": "RIOB18_X312Y232"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y225\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y225\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y235",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y226\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y226\"",
|
|
"TILE_NAME": "RIOB18_X312Y235"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y228\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y228\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y237",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y227\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y227\"",
|
|
"TILE_NAME": "RIOB18_X312Y237"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y230\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y230\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y239",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y229\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y229\"",
|
|
"TILE_NAME": "RIOB18_X312Y239"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y232\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y232\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y241",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y231\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y231\"",
|
|
"TILE_NAME": "RIOB18_X312Y241"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y234\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y234\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y243",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y233\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y233\"",
|
|
"TILE_NAME": "RIOB18_X312Y243"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 2,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y236\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y236\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y245",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y235\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y235\"",
|
|
"TILE_NAME": "RIOB18_X312Y245"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y237\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y237\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y247",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y238\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y238\"",
|
|
"TILE_NAME": "RIOB18_X312Y247"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y239\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y239\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y249",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y240\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y240\"",
|
|
"TILE_NAME": "RIOB18_X312Y249"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y241\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y241\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y251",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y242\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y242\"",
|
|
"TILE_NAME": "RIOB18_X312Y251"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y243\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y243\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y253",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y244\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y244\"",
|
|
"TILE_NAME": "RIOB18_X312Y253"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y246\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y246\"",
|
|
"TILE_NAME": "RIOB18_X312Y255"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y245\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y245\"",
|
|
"TILE_NAME": "RIOB18_X312Y255"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y247\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y247\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y257",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y248\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y248\"",
|
|
"TILE_NAME": "RIOB18_X312Y257"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y252\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y252\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y262",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y251\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y251\"",
|
|
"TILE_NAME": "RIOB18_X312Y262"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y253\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y253\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y264",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y254\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y254\"",
|
|
"TILE_NAME": "RIOB18_X312Y264"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y256\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y256\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y266",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y255\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y255\"",
|
|
"TILE_NAME": "RIOB18_X312Y266"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y258\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y258\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y268",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y257\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y257\"",
|
|
"TILE_NAME": "RIOB18_X312Y268"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y260\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y260\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y270",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y259\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y259\"",
|
|
"TILE_NAME": "RIOB18_X312Y270"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y261\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y261\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y272",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y262\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y262\"",
|
|
"TILE_NAME": "RIOB18_X312Y272"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y264\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y264\"",
|
|
"TILE_NAME": "RIOB18_X312Y274"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y263\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y263\"",
|
|
"TILE_NAME": "RIOB18_X312Y274"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y266\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y266\"",
|
|
"TILE_NAME": "RIOB18_X312Y276"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y265\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y265\"",
|
|
"TILE_NAME": "RIOB18_X312Y276"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y268\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y268\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y278",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y267\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y267\"",
|
|
"TILE_NAME": "RIOB18_X312Y278"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y270\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y270\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y280",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y269\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y269\"",
|
|
"TILE_NAME": "RIOB18_X312Y280"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y272\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y272\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y282",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y271\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y271\"",
|
|
"TILE_NAME": "RIOB18_X312Y282"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y273\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y273\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y284",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y274\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y274\"",
|
|
"TILE_NAME": "RIOB18_X312Y284"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y276\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y276\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y287",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y275\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y275\"",
|
|
"TILE_NAME": "RIOB18_X312Y287"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y278\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y278\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y289",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y277\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y277\"",
|
|
"TILE_NAME": "RIOB18_X312Y289"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y279\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y279\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y291",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y280\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y280\"",
|
|
"TILE_NAME": "RIOB18_X312Y291"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y282\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y282\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y293",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y281\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y281\"",
|
|
"TILE_NAME": "RIOB18_X312Y293"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y283\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y283\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y295",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y284\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y284\"",
|
|
"TILE_NAME": "RIOB18_X312Y295"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y286\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y286\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y297",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y285\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y285\"",
|
|
"TILE_NAME": "RIOB18_X312Y297"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y287\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y287\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y299",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y288\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y288\"",
|
|
"TILE_NAME": "RIOB18_X312Y299"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y289\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y289\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y301",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y290\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y290\"",
|
|
"TILE_NAME": "RIOB18_X312Y301"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y292\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y292\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y303",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y291\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y291\"",
|
|
"TILE_NAME": "RIOB18_X312Y303"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y294\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y294\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y305",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y293\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y293\"",
|
|
"TILE_NAME": "RIOB18_X312Y305"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y296\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_QDR\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y296\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y307",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y295\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y295\"",
|
|
"TILE_NAME": "RIOB18_X312Y307"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y298\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y298\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 1,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y309",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y297\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y297\"",
|
|
"TILE_NAME": "RIOB18_X312Y309"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y301\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y301\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y314",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y302\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y302\"",
|
|
"TILE_NAME": "RIOB18_X312Y314"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 3,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y303\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y303\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y316",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y304\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y304\"",
|
|
"TILE_NAME": "RIOB18_X312Y316"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y305\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"BOTH\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y305\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y318",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y306\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y306\"",
|
|
"TILE_NAME": "RIOB18_X312Y318"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y308\"",
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y308\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y320",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y307\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y307\"",
|
|
"TILE_NAME": "RIOB18_X312Y320"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y310\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y310\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y322",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y309\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y309\"",
|
|
"TILE_NAME": "RIOB18_X312Y322"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y311\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y311\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y324",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y312\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y312\"",
|
|
"TILE_NAME": "RIOB18_X312Y324"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y313\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y313\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y326",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y314\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y314\"",
|
|
"TILE_NAME": "RIOB18_X312Y326"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y316\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y316\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"RST\"",
|
|
"TILE_NAME": "RIOB18_X312Y328",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y315\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y315\"",
|
|
"TILE_NAME": "RIOB18_X312Y328"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y318\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y318\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y330",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y317\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y317\"",
|
|
"TILE_NAME": "RIOB18_X312Y330"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y320\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y320\"",
|
|
"TILE_NAME": "RIOB18_X312Y332"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y319\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y319\"",
|
|
"TILE_NAME": "RIOB18_X312Y332"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y322\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y322\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y334",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y321\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y321\"",
|
|
"TILE_NAME": "RIOB18_X312Y334"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 5,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y323\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 1,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y323\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y336",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y324\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y324\"",
|
|
"TILE_NAME": "RIOB18_X312Y336"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y326\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y326\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y339",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y325\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y325\"",
|
|
"TILE_NAME": "RIOB18_X312Y339"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y328\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"TRUE\"",
|
|
"SERDES_MODE": "\"SLAVE\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y328\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 0,
|
|
"TILE_NAME": "RIOB18_X312Y341",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y327\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y327\"",
|
|
"TILE_NAME": "RIOB18_X312Y341"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y330\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y330\"",
|
|
"TILE_NAME": "RIOB18_X312Y343"
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y329\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y329\"",
|
|
"TILE_NAME": "RIOB18_X312Y343"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 1,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y331\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y331\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y345",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y332\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y332\"",
|
|
"TILE_NAME": "RIOB18_X312Y345"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y333\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 0,
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y333\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"NONE\"",
|
|
"TILE_NAME": "RIOB18_X312Y347",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y334\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y334\"",
|
|
"TILE_NAME": "RIOB18_X312Y347"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y335\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y335\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y349",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y336\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y336\"",
|
|
"TILE_NAME": "RIOB18_X312Y349"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"DDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"FALSE\"",
|
|
"DYN_CLK_INV_EN": "\"TRUE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y338\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"OVERSAMPLE\"",
|
|
"IOBDELAY": "\"IBUF\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 1,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y338\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 1,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y351",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y337\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y337\"",
|
|
"TILE_NAME": "RIOB18_X312Y351"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y340\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y340\"",
|
|
"SRTYPE": "\"ASYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y353",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y339\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y339\"",
|
|
"TILE_NAME": "RIOB18_X312Y353"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 4,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y341\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 1,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 0,
|
|
"INTERFACE_TYPE": "\"MEMORY_DDR3\"",
|
|
"IOBDELAY": "\"IFD\"",
|
|
"IS_CLKB_INVERTED": 1,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 1,
|
|
"IS_CLK_INVERTED": 0,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 1,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 2,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y341\"",
|
|
"SRVAL_Q1": 0,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y355",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y342\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y342\"",
|
|
"TILE_NAME": "RIOB18_X312Y355"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"ISERDESE2\"",
|
|
"CHAINED": 0,
|
|
"DATA_RATE": "\"SDR\"",
|
|
"DATA_WIDTH": 2,
|
|
"DYN_CLKDIV_INV_EN": "\"TRUE\"",
|
|
"DYN_CLK_INV_EN": "\"FALSE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y344\"",
|
|
"INIT_Q1": 0,
|
|
"INIT_Q2": 0,
|
|
"INIT_Q3": 0,
|
|
"INIT_Q4": 1,
|
|
"INTERFACE_TYPE": "\"NETWORKING\"",
|
|
"IOBDELAY": "\"NONE\"",
|
|
"IS_CLKB_INVERTED": 0,
|
|
"IS_CLKDIVP_INVERTED": 0,
|
|
"IS_CLKDIV_INVERTED": 0,
|
|
"IS_CLK_INVERTED": 1,
|
|
"IS_D_INVERTED": 1,
|
|
"IS_OCLKB_INVERTED": 0,
|
|
"IS_OCLK_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"NUM_CE": 1,
|
|
"OFB_USED": "\"FALSE\"",
|
|
"SERDES_MODE": "\"MASTER\"",
|
|
"SITE_LOC": "\"ILOGIC_X1Y344\"",
|
|
"SRVAL_Q1": 1,
|
|
"SRVAL_Q2": 0,
|
|
"SRVAL_Q3": 0,
|
|
"SRVAL_Q4": 1,
|
|
"TILE_NAME": "RIOB18_X312Y357",
|
|
"USE_IDELAY": 0
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y343\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y343\"",
|
|
"TILE_NAME": "RIOB18_X312Y357"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR_NO_CLK\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y345\"",
|
|
"IDELMUX": 1,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 1,
|
|
"IS_C_INVERTED": 1,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y345\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y359",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y346\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y346\"",
|
|
"TILE_NAME": "RIOB18_X312Y359"
|
|
}
|
|
],
|
|
[
|
|
{
|
|
"BEL_TYPE": "\"IDDR\"",
|
|
"CE1USED": 0,
|
|
"CHAINED": 0,
|
|
"DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"",
|
|
"IDELAY_LOC": "\"IDELAY_X1Y347\"",
|
|
"IDELMUX": 0,
|
|
"IFFDELMUX": 1,
|
|
"INIT_Q1": 1,
|
|
"INIT_Q2": 0,
|
|
"IS_C_INVERTED": 0,
|
|
"IS_D_INVERTED": 0,
|
|
"IS_USED": 1,
|
|
"SITE_LOC": "\"ILOGIC_X1Y347\"",
|
|
"SRTYPE": "\"SYNC\"",
|
|
"SR_MODE": "\"SET\"",
|
|
"TILE_NAME": "RIOB18_X312Y361",
|
|
"USE_IDELAY": 1
|
|
},
|
|
{
|
|
"IDELAY_LOC": "\"IDELAY_X1Y348\"",
|
|
"IS_USED": 0,
|
|
"SITE_LOC": "\"ILOGIC_X1Y348\"",
|
|
"TILE_NAME": "RIOB18_X312Y361"
|
|
}
|
|
]
|
|
] |