mirror of https://github.com/openXC7/prjxray.git
39 lines
630 B
Verilog
39 lines
630 B
Verilog
module top(input clk, stb, di, output do);
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wire [5:0] I;
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wire LUT_O;
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wire FF_Q;
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localparam SIG_MASK = `SIG_MASK;
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genvar i;
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generate for(i = 0; i < 6; i = i + 1) begin : loop
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if(((1 << i) & SIG_MASK) != 0) begin
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assign I[i] = FF_Q;
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end else begin
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assign I[i] = 1;
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end
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end endgenerate
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(* LOC="SLICE_X37Y74", BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6 lut(
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.I0(I[0]),
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.I1(I[1]),
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.I2(I[2]),
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.I3(I[3]),
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.I4(I[4]),
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.I5(I[5]),
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.O(LUT_O)
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);
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(* LOC="SLICE_X37Y74", BEL="DFF", KEEP, DONT_TOUCH *)
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FDRE ff(
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.C(clk),
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.R(0),
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.CE(1),
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.D(LUT_O),
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.Q(FF_Q)
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);
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endmodule
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