mirror of https://github.com/openXC7/prjxray.git
48 lines
1.3 KiB
Tcl
48 lines
1.3 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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source ../../utils/utils.tcl
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proc print_tile_info {tile} {
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puts "Dumping wires and PIPs for tile $tile."
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set fp [open "wires_${tile}.txt" w]
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foreach wire [lsort [get_wires -of_objects [get_tiles $tile]]] {
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puts $fp [regsub {.*/} $wire ""]
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}
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close $fp
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set fp [open "pips_${tile}.txt" w]
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foreach wire [lsort [get_pips -of_objects [get_tiles $tile]]] {
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puts $fp [regsub {.*/} $wire ""]
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}
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close $fp
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}
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foreach tile [lsort [get_tiles]] {
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print_tile_info $tile
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}
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