mirror of https://github.com/openXC7/prjxray.git
45 lines
616 B
Verilog
45 lines
616 B
Verilog
module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire Q
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);
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wire q31_d;
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wire q31_c;
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(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
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SRLC32E srl_d
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q31 (q31_d)
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);
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(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
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SRLC32E srl_c
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_d),
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.A (A),
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.Q31 (q31_c)
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);
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (q31_c),
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.A (A),
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.Q (Q)
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);
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endmodule
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