mirror of https://github.com/openXC7/prjxray.git
64 lines
993 B
Verilog
64 lines
993 B
Verilog
module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [5:0] I,
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input wire [4:0] A,
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output wire [3:0] Q
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);
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wire srl_b_mc31;
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wire srl_c_mc31;
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(* DONT_TOUCH="yes" *)
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (srl_b_mc31),
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.A (A),
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.Q (Q[0])
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);
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(* DONT_TOUCH="yes" *)
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (srl_c_mc31),
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.A (A),
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.Q (Q[1]),
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.Q31 (srl_b_mc31)
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);
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(* DONT_TOUCH="yes" *)
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(* LOC="SLICE_X2Y0", BEL="C6LUT" *)
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SRLC32E srl_c
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[2]),
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.Q31 (srl_c_mc31)
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);
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(* DONT_TOUCH="yes" *)
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(* LOC="SLICE_X2Y0", BEL="D6LUT" *)
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LUT6 lut_d
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(
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.I0 (I[0]),
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.I1 (I[1]),
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.I2 (I[2]),
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.I3 (I[3]),
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.I4 (I[4]),
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.I5 (I[5]),
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.O (Q[3])
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);
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endmodule
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