mirror of https://github.com/openXC7/prjxray.git
32 lines
439 B
Verilog
32 lines
439 B
Verilog
module top
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(
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(* clock_buffer_type = "NONE" *)
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input wire CLK,
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input wire CE,
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input wire D,
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input wire [4:0] A,
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output wire [1:0] Q
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);
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(* LOC="SLICE_X2Y0", BEL="A6LUT" *)
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SRLC32E srl_a
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[0])
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);
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(* LOC="SLICE_X2Y0", BEL="B6LUT" *)
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SRLC32E srl_b
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(
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.CLK (CLK),
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.CE (CE),
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.D (D),
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.A (A),
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.Q (Q[1])
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);
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endmodule
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