mirror of https://github.com/openXC7/prjxray.git
150 lines
3.5 KiB
Verilog
150 lines
3.5 KiB
Verilog
//See README and tcl for more info
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`default_nettype none
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`include "defines.v"
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module roi(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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wire [DIN_N-1:0] din_lut;
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wire [DOUT_N-1:0] dout_lut;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(din_lut[i]));
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(dout_lut[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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demoscene demoscene(.clk(clk), .din(din_lut), .dout(dout_lut));
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endmodule
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module demoscene(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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//assign dout = 8'b10101010;
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demoscene_scroll dut(.clk(clk), .din(din), .dout(dout));
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endmodule
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/*
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Leftmost LED counts at one second
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*/
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module demoscene_counter(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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/*
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100 MHz clock
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Lets get MSB to 1 second
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Need 27 bits
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In [3]: math.log(100e6, 2)
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Out[3]: 26.5754247590989
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*/
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reg [26:0] div;
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always @(posedge clk) begin
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div <= div + 1'b1;
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end
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assign dout = div[26:19];
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endmodule
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//Loosely based on http://www.asic-world.com/code/hdl_models/lfsr.v
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module lfsr(input wire clk, output wire dout);
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reg [7:0] out = 8'hAA;
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wire feedback = !(out[7] ^ out[3]);
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always @(posedge clk) begin
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out <= {out[6],out[5],
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out[4],out[3],
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out[2],out[1],
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out[0], feedback};
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end
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assign dout = out[0];
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endmodule
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// http://www.fpga4fun.com/Counters3.html
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module lfsr2(input wire clk, output wire dout);
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reg [7:0] LFSR = 255;
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wire feedback = LFSR[7];
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assign dout = LFSR[0];
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always @(posedge clk) begin
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LFSR[0] <= feedback;
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LFSR[1] <= LFSR[0];
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LFSR[2] <= LFSR[1] ^ feedback;
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LFSR[3] <= LFSR[2] ^ feedback;
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LFSR[4] <= LFSR[3] ^ feedback;
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LFSR[5] <= LFSR[4];
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LFSR[6] <= LFSR[5];
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LFSR[7] <= LFSR[6];
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end
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endmodule
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/*
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Scrolls an LSFR across
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*/
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module demoscene_scroll(input wire clk,
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input wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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reg [26:0] div;
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always @(posedge clk) begin
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div <= div + 1'b1;
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end
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wire randbit;
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lfsr2 lfsr(.clk(clk), .dout(randbit));
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reg [7:0] leds = 8'hCC;
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reg last;
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reg tick;
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always @(posedge clk) begin
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last <= div[23];
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tick <= div[23] ^ last;
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if (tick) begin
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leds = {leds, randbit};
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end
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end
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assign dout = leds;
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endmodule
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