mirror of https://github.com/openXC7/prjxray.git
66 lines
1.4 KiB
Verilog
66 lines
1.4 KiB
Verilog
//See README and tcl for more info
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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wire div_clk;
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wire clk_IBUF_BUFG;
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BUFR #(
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.BUFR_DIVIDE(2)
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) clock_divider (
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.I(clk),
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.O(div_clk),
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.CE(1),
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.CLR(0)
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);
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BUFG clock_buffer (
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.I(div_clk),
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.O(clk_IBUF_BUFG)
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);
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk_IBUF_BUFG) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O());
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(1'b0),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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