mirror of https://github.com/openXC7/prjxray.git
56 lines
909 B
Verilog
56 lines
909 B
Verilog
`include "src/plle2_test.v"
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`default_nettype none
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// ============================================================================
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module top
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(
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input wire clk,
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input wire rx,
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output wire tx,
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input wire [15:0] sw,
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output wire [15:0] led
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);
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// ============================================================================
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assign tx = rx;
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// ============================================================================
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// Clock & reset
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge clk)
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if (sw[0])
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rst_sr <= 4'hF;
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else
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rst_sr <= rst_sr >> 1;
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wire CLK = clk;
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wire RST = rst_sr[0];
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// ============================================================================
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// The tester
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plle2_test plle2_test
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(
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.CLK (CLK),
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.RST (RST),
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.I_CLKINSEL (sw[1]),
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.O_LOCKED (led[15]),
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.O_CNT (led[5:0])
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);
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assign led [14] = |sw;
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assign led [13:6] = 0;
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endmodule
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