mirror of https://github.com/openXC7/prjxray.git
19 lines
434 B
Verilog
19 lines
434 B
Verilog
`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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endmodule
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module top(input wire clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N)) roi (
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.clk(clk),
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.din(din), .dout(dout));
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endmodule
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