mirror of https://github.com/openXC7/prjxray.git
72 lines
1.3 KiB
Verilog
72 lines
1.3 KiB
Verilog
`include "../src/oserdes_test.v"
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`include "../src/lfsr.v"
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`include "../src/comparator.v"
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`default_nettype none
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`timescale 1ns / 1ps
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// ============================================================================
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module tb;
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// ============================================================================
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reg CLK;
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initial CLK <= 1'b0;
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always #0.5 CLK <= !CLK;
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge CLK) rst_sr <= rst_sr >> 1;
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wire RST;
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assign RST = rst_sr[0];
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// ============================================================================
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initial begin
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$dumpfile("waveforms.vcd");
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$dumpvars;
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end
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integer cycle_cnt;
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initial cycle_cnt <= 0;
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always @(posedge CLK)
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if (!RST) cycle_cnt <= cycle_cnt + 1;
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always @(posedge CLK)
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if (!RST && cycle_cnt >= 10000)
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$finish;
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// ============================================================================
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reg clk_r;
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always @(posedge CLK)
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if (RST) clk_r <= 1'b0;
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else clk_r <= !clk_r;
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wire CLK1 = CLK;
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wire CLK2 = clk_r;
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// ============================================================================
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wire s_dat;
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oserdes_test #
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(
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.DATA_WIDTH (8),
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.DATA_RATE ("SDR"),
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.ERROR_HOLD (4)
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)
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trx_path
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(
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.CLK (CLK),
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.CLK1 (CLK1),
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.CLK2 (CLK2),
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.RST (RST),
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.IO_DAT (s_dat)
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);
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endmodule
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